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xc7_bram.v	fix: BRAM being written to via read port	2024-12-29 20:36:55 +01:00

README.md

pixelflutrinnsal

Pixelflut on an FPGA with an active area of 346 by 196 pixels (video format 640x480 at ~60Hz)

The Ethernet PHY on the Arty A7 is limited to 100Mbit/s, so use less bandwidth!

"Protocol"

see GPN17:Pingxelflut

Do not expect to get an ICMPv6 Echo Reply, as only the receiver is implemented :D

Routing

This is meant only as a reference for setting up the system directly connected to the FPGA board. You do not need to run these commands on your machine.

ip a add 2001:db8::ffff:ffff:0:2/64 dev eth0
ip neigh add 2001:db8::ffff:ffff:0:1 lladdr 02:00:00:00:00:00 dev eth0
ip r add 2001:db8::/64 via 2001:db8::ffff:ffff:0:1 dev eth0
ip r del 2001:db8::/64 dev eth0