43 lines
661 B
Verilog
43 lines
661 B
Verilog
`timescale 1 ns / 1 ns
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module testbench();
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reg clk = 0;
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always #20 clk = ~clk;
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reg [3:0] rxd;
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wire bus_clk;
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wire [15:0] bus_data;
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wire [23:0] bus_addr;
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wire [1:0] bus_sel;
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pingxelflut eth (
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.rx_clk (clk),
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.rxd (rxd),
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.rx_dv (1'b1),
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.rx_er (1'b0),
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.bus_clk (bus_clk),
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.bus_data(bus_data),
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.bus_addr(bus_addr),
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.bus_sel (bus_sel)
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);
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reg [3:0] test_data [0:128];
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initial begin
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$dumpfile("pingxelflut_tb.vcd");
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$dumpvars(0, testbench);
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$readmemh("pingxelflut_tb.hex", test_data);
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rxd <= test_data[0];
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#10;
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for (integer i = 1; i < 129; i = i + 1) #40 rxd <= test_data[i];
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$finish;
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end
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endmodule
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