`timescale 1 ns / 1 ns

module testbench();
	reg clk = 0;

	always #20 clk = ~clk;

	reg [3:0] rxd;

	wire        bus_clk;
	wire [15:0] bus_data;
	wire [23:0] bus_addr;
	wire  [1:0] bus_sel;

	pingxelflut eth (
		.rx_clk  (clk),
		.rxd     (rxd),
		.rx_dv   (1'b1),
		.rx_er   (1'b0),

		.bus_clk (bus_clk),
		.bus_data(bus_data),
		.bus_addr(bus_addr),
		.bus_sel (bus_sel)
	);

	reg [3:0] test_data [0:128];

	initial begin
		$dumpfile("pingxelflut_tb.vcd");
		$dumpvars(0, testbench);

		$readmemh("pingxelflut_tb.hex", test_data);

		rxd <= test_data[0];
		#10;
		for (integer i = 1; i < 129; i = i + 1) #40 rxd <= test_data[i];

		$finish;
	end
endmodule