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fix: pixel addressing

This commit is contained in:
Luca 2024-12-29 20:21:17 +01:00
parent d7b46ab41c
commit 3e3306bca3
1 changed files with 11 additions and 7 deletions
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18
pingxelflut.v
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@ -84,13 +84,17 @@ module pingxelflut #(
reg [6:0] state;
reg broadcast;
reg [22:0] pixel_addr;
reg [23:0] pixel_addr;
reg [16:0] pixel_data;
wire maybe_broadcast;
assign maybe_broadcast = broadcast && rxd == 4'hf;
wire [23:0] base_addr;
assign base_addr = pixel_addr * 3 >> 1;
initial begin
bus_clk <= 0;
bus_data <= 16'b0;
@ -99,7 +103,7 @@ module pingxelflut #(
state <= PREAMBLE;
broadcast <= 0;
pixel_addr <= 23'b0;
pixel_addr <= 24'b0;
pixel_data <= 16'b0;
end
@ -153,7 +157,7 @@ module pingxelflut #(
pixel_data[ 3:0] <= rxd;
end else begin
bus_data <= pixel_data;
bus_addr <= {pixel_addr, 1'b1};
bus_addr <= base_addr + 1;
bus_sel <= 2'b01;
pixel_data[11:8] <= rxd;
@ -171,7 +175,7 @@ module pingxelflut #(
BLUE_LOW: begin
if (pixel_addr[0]) begin
bus_data <= pixel_data;
bus_addr <= {pixel_addr, 1'b0};
bus_addr <= base_addr + 1;
bus_sel <= 2'b11;
pixel_data[11:8] <= rxd;
@ -195,10 +199,10 @@ module pingxelflut #(
if (pixel_addr[0]) begin
bus_clk <= 0;
bus_addr <= {pixel_addr, 1'b1};
bus_addr <= base_addr;
bus_sel <= 2'b10;
end else begin
bus_addr <= {pixel_addr, 1'b0};
bus_addr <= base_addr;
bus_sel <= 2'b11;
end
end
@ -209,7 +213,7 @@ module pingxelflut #(
bus_clk <= 0;
state <= PREAMBLE;
pixel_addr <= 23'b0;
pixel_addr <= 24'b0;
pixel_data <= 16'b0;
end
end