From 3e3306bca30a4b0d57042a2b734db4d48b10154f Mon Sep 17 00:00:00 2001 From: Luca Date: Sun, 29 Dec 2024 20:21:17 +0100 Subject: [PATCH] fix: pixel addressing --- pingxelflut.v | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/pingxelflut.v b/pingxelflut.v index 6792abd..e45cc65 100644 --- a/pingxelflut.v +++ b/pingxelflut.v @@ -84,13 +84,17 @@ module pingxelflut #( reg [6:0] state; reg broadcast; - reg [22:0] pixel_addr; + reg [23:0] pixel_addr; reg [16:0] pixel_data; wire maybe_broadcast; assign maybe_broadcast = broadcast && rxd == 4'hf; + wire [23:0] base_addr; + + assign base_addr = pixel_addr * 3 >> 1; + initial begin bus_clk <= 0; bus_data <= 16'b0; @@ -99,7 +103,7 @@ module pingxelflut #( state <= PREAMBLE; broadcast <= 0; - pixel_addr <= 23'b0; + pixel_addr <= 24'b0; pixel_data <= 16'b0; end @@ -153,7 +157,7 @@ module pingxelflut #( pixel_data[ 3:0] <= rxd; end else begin bus_data <= pixel_data; - bus_addr <= {pixel_addr, 1'b1}; + bus_addr <= base_addr + 1; bus_sel <= 2'b01; pixel_data[11:8] <= rxd; @@ -171,7 +175,7 @@ module pingxelflut #( BLUE_LOW: begin if (pixel_addr[0]) begin bus_data <= pixel_data; - bus_addr <= {pixel_addr, 1'b0}; + bus_addr <= base_addr + 1; bus_sel <= 2'b11; pixel_data[11:8] <= rxd; @@ -195,10 +199,10 @@ module pingxelflut #( if (pixel_addr[0]) begin bus_clk <= 0; - bus_addr <= {pixel_addr, 1'b1}; + bus_addr <= base_addr; bus_sel <= 2'b10; end else begin - bus_addr <= {pixel_addr, 1'b0}; + bus_addr <= base_addr; bus_sel <= 2'b11; end end @@ -209,7 +213,7 @@ module pingxelflut #( bus_clk <= 0; state <= PREAMBLE; - pixel_addr <= 23'b0; + pixel_addr <= 24'b0; pixel_data <= 16'b0; end end