61 lines
1.1 KiB
Verilog
61 lines
1.1 KiB
Verilog
module pixelflut (
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input sys_clk,
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output led0_r,
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output led0_g,
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output led0_b,
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output [11:0] dvi_d,
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output dvi_ck,
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output dvi_de,
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output dvi_hs,
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output dvi_vs,
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);
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reg [31:0] ctr;
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reg [2:0] led0_state = 3'b0;
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assign led0_r = led0_state[0];
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assign led0_g = led0_state[1];
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assign led0_b = led0_state[2];
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always @(posedge sys_clk) begin
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if (ctr == 32'd50_000_000) begin
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ctr <= 32'b0;
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led0_state <= led0_state + 1'b1;
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end else begin
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ctr <= ctr + 1'b1;
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end
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end
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reg dvi_bus_clk;
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always @(posedge sys_clk) begin
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dvi_bus_clk <= ~dvi_bus_clk;
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end
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wire [15:0] dvi_bus_data;
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wire [23:0] dvi_bus_addr;
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dvi display (
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.bus_clk (dvi_bus_clk),
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.bus_data(dvi_bus_data),
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.bus_addr(dvi_bus_addr),
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.reset (1'b0),
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.d (dvi_d),
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.ck (dvi_ck),
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.de (dvi_de),
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.hs (dvi_hs),
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.vs (dvi_vs),
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);
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xc7_bram ram (
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.out_clk (dvi_bus_clk),
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.out_data(dvi_bus_data),
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.out_addr(dvi_bus_addr),
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.in_clk (),
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.in_data (),
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.in_addr (),
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.in_wren (),
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);
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endmodule
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