29 lines
394 B
Verilog
29 lines
394 B
Verilog
module ethernet_smi #(
|
|
parameter CLK_DIVIDE = 10,
|
|
) (
|
|
input clk,
|
|
|
|
input mdio_i,
|
|
output reg mdio_o,
|
|
output reg mdio_en,
|
|
output reg mdc,
|
|
);
|
|
reg [3:0] ctr;
|
|
|
|
initial begin
|
|
mdio_o <= 1'b1;
|
|
mdio_en <= 1'b0;
|
|
|
|
ctr <= 4'b0;
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
if (ctr == CLK_DIVIDE) begin
|
|
mdc <= ~mdc;
|
|
ctr <= 4'b0;
|
|
end else begin
|
|
ctr <= ctr + 1;
|
|
end
|
|
end
|
|
endmodule
|