33 lines
437 B
Verilog
33 lines
437 B
Verilog
`timescale 1 ns / 1 ns
|
|
|
|
module testbench();
|
|
reg clk = 0;
|
|
|
|
always #10 clk = ~clk;
|
|
|
|
wire [15:0] addr;
|
|
wire [11:0] d;
|
|
wire ck, de, hs, vs;
|
|
|
|
dvi display (
|
|
.bus_clk (clk),
|
|
.bus_data(addr),
|
|
.bus_addr(addr),
|
|
|
|
.reset (1'b0),
|
|
|
|
.d (d),
|
|
.ck (ck),
|
|
.de (de),
|
|
.hs (hs),
|
|
.vs (vs)
|
|
);
|
|
|
|
initial begin
|
|
$dumpfile("dvi_tb.vcd");
|
|
$dumpvars(0, testbench);
|
|
#16800040;
|
|
$finish;
|
|
end
|
|
endmodule
|