33 lines
437 B
Coq
33 lines
437 B
Coq
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`timescale 1 ns / 1 ns
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module testbench();
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reg clk = 0;
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always #10 clk = ~clk;
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wire [15:0] addr;
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wire [11:0] d;
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wire ck, de, hs, vs;
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dvi display (
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.bus_clk (clk),
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.bus_data(addr),
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.bus_addr(addr),
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.reset (1'b0),
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.d (d),
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.ck (ck),
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.de (de),
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.hs (hs),
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.vs (vs)
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);
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initial begin
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$dumpfile("dvi_tb.vcd");
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$dumpvars(0, testbench);
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#16800040;
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$finish;
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end
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endmodule
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