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pixelflut
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Verilog 34.7%
Makefile 2.7%
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Luca 2b263e297a build: add make target for writing bitstream to flash 2024-12-29 21:02:01 +01:00
.gitignore chore: add testbench for dvi module 2024-10-19 00:07:55 +02:00
Makefile build: add make target for writing bitstream to flash 2024-12-29 21:02:01 +01:00
README.md docs: add README.md 2024-10-19 00:11:26 +02:00
arty_a7_35t.xdc feat: add display driver 2024-10-19 00:02:00 +02:00
ddr3l.v refactor: group DDR3L pins 2024-10-18 23:45:34 +02:00
dvi.v refactor(dvi): change default parameters to 346x196 data 2024-12-29 02:30:28 +01:00
dvi_tb.v chore(dvi_tb): increase addr width to 24 2024-12-29 01:58:35 +01:00
ethernet_smi.v feat: implement Pingxelflut "protocol" 2024-12-29 16:28:35 +01:00
fetch_state.txt chore: add testbench for dvi module 2024-10-19 00:07:55 +02:00
output_state.txt chore: add testbench for dvi module 2024-10-19 00:07:55 +02:00
pingxelflut.v fix: pixel addressing 2024-12-29 20:21:17 +01:00
pingxelflut_state.txt test(pingxelflut): add testbench 2024-12-29 18:32:08 +01:00
pingxelflut_tb.hex test(pingxelflut): add testbench 2024-12-29 18:32:08 +01:00
pingxelflut_tb.v test(pingxelflut): add testbench 2024-12-29 18:32:08 +01:00
pixelflut.v feat: implement Pingxelflut "protocol" 2024-12-29 16:28:35 +01:00
xc7_bram.v fix: BRAM being written to via read port 2024-12-29 20:36:55 +01:00

README.md

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