fix: BRAM being written to via read port

Makefile

@@ -14,7 +14,7 @@ clean:
 prog: pixelflut.bit
 	openFPGALoader -b arty_a7_35t $<
 
-sim: dvi_tb.vcd
+sim: dvi_tb.vcd pingxelflut_tb.vcd
 
 pixelflut.bit: pixelflut.frames
 	xc7frames2bit --part_file "$(XRAY_DATABASE_DIR)/artix7/$(PART)/part.yaml" --part_name $(PART) --frm_file $< --output_file $@
@@ -25,7 +25,7 @@ pixelflut.frames: pixelflut.fasm
 pixelflut.fasm: arty_a7_35t.xdc pixelflut.json
 	nextpnr-xilinx --chipdb "$(CHIPDB_DIR)/$(PART).bin" --fasm $@ --json pixelflut.json --xdc arty_a7_35t.xdc
 
-pixelflut.json: pixelflut.v dvi.v xc7_bram.v
+pixelflut.json: pixelflut.v dvi.v ethernet_smi.v pingxelflut.v xc7_bram.v
 	yosys -q -p 'synth_xilinx -top pixelflut; write_json $@' $^
 
 dvi_tb.vcd: dvi_tb.vvp
@@ -33,3 +33,9 @@ dvi_tb.vcd: dvi_tb.vvp
 
 dvi_tb.vvp: dvi_tb.v dvi.v
 	iverilog -o $@ $^
+
+pingxelflut_tb.vcd: pingxelflut_tb.vvp
+	vvp $<
+
+pingxelflut_tb.vvp: pingxelflut_tb.v pingxelflut.v
+	iverilog -o $@ $^

ethernet_smi.v

@@ -0,0 +1,28 @@
+module ethernet_smi #(
+	parameter CLK_DIVIDE = 10,
+) (
+	input      clk,
+
+	input      mdio_i,
+	output reg mdio_o,
+	output reg mdio_en,
+	output reg mdc,
+);
+	reg [3:0] ctr;
+
+	initial begin
+		mdio_o <= 1'b1;
+		mdio_en <= 1'b0;
+
+		ctr <= 4'b0;
+	end
+
+	always @(posedge clk) begin
+		if (ctr == CLK_DIVIDE) begin
+			mdc <= ~mdc;
+			ctr <= 4'b0;
+		end else begin
+			ctr <= ctr + 1;
+		end
+	end
+endmodule

pingxelflut.v

@@ -0,0 +1,220 @@
+module pingxelflut #(
+	parameter MAC_ADDRESS = 48'h02_00_00_00_00_00,
+
+	parameter SCREEN_WIDTH = 346
+) (
+	input             rx_clk,
+	input       [3:0] rxd,
+	input             rx_dv,
+	input             rx_er,
+
+	output reg        bus_clk,
+	output reg [15:0] bus_data,
+	output reg [23:0] bus_addr,
+	output reg  [1:0] bus_sel
+);
+	localparam PREAMBLE          = 7'b0000000;
+	localparam DEST_0            = 7'b0000001;
+	localparam DEST_1            = 7'b0000010;
+	localparam DEST_2            = 7'b0000011;
+	localparam DEST_3            = 7'b0000100;
+	localparam DEST_4            = 7'b0000101;
+	localparam DEST_5            = 7'b0000110;
+	localparam DEST_6            = 7'b0000111;
+	localparam DEST_7            = 7'b0001000;
+	localparam DEST_8            = 7'b0001001;
+	localparam DEST_9            = 7'b0001010;
+	localparam DEST_A            = 7'b0001011;
+	localparam DEST_B            = 7'b0001100;
+	localparam SRC_0             = 7'b0001101;
+	localparam SRC_1             = 7'b0001110;
+	localparam SRC_2             = 7'b0001111;
+	localparam SRC_3             = 7'b0010000;
+	localparam SRC_4             = 7'b0010001;
+	localparam SRC_5             = 7'b0010010;
+	localparam SRC_6             = 7'b0010011;
+	localparam SRC_7             = 7'b0010100;
+	localparam SRC_8             = 7'b0010101;
+	localparam SRC_9             = 7'b0010110;
+	localparam SRC_A             = 7'b0010111;
+	localparam SRC_B             = 7'b0011000;
+	localparam ETHER_TYPE_0      = 7'b0011001;
+	localparam ETHER_TYPE_1      = 7'b0011010;
+	localparam ETHER_TYPE_2      = 7'b0011011;
+	localparam ETHER_TYPE_3      = 7'b0011100;
+
+	localparam TRAFFIC_CLASS_0   = 7'b0100000;
+	localparam VERSION           = 7'b0100001;
+	localparam FLOW_LABEL_0      = 7'b0100010;
+	localparam TRAFFIC_CLASS_1   = 7'b0100011;
+	localparam FLOW_LABEL_1      = 7'b0100100;
+	localparam FLOW_LABEL_2      = 7'b0100101;
+	localparam FLOW_LABEL_3      = 7'b0100110;
+	localparam FLOW_LABEL_4      = 7'b0100111;
+	localparam PAYLOAD_LENGTH_0  = 7'b0101000;
+	localparam PAYLOAD_LENGTH_1  = 7'b0101001;
+	localparam PAYLOAD_LENGTH_2  = 7'b0101010;
+	localparam PAYLOAD_LENGTH_3  = 7'b0101011;
+	localparam NEXT_HEADER_0     = 7'b0101100;
+	localparam NEXT_HEADER_1     = 7'b0101101;
+	localparam HOP_LIMIT_0       = 7'b0101110;
+	localparam HOP_LIMIT_1       = 7'b0101111;
+	localparam SRC_ADDR_0        = 7'b0110000;
+	localparam DEST_PREFIX_0     = 7'b1010000;
+	localparam X_0               = 7'b1100000;
+	localparam X_1               = 7'b1100001;
+	localparam X_2               = 7'b1100010;
+	localparam X_3               = 7'b1100011;
+	localparam Y_0               = 7'b1100100;
+	localparam Y_1               = 7'b1100101;
+	localparam Y_2               = 7'b1100110;
+	localparam Y_3               = 7'b1100111;
+	localparam RED_LOW           = 7'b1101000;
+	localparam RED_HIGH          = 7'b1101001;
+	localparam GREEN_LOW         = 7'b1101010;
+	localparam GREEN_HIGH        = 7'b1101011;
+	localparam BLUE_LOW          = 7'b1101100;
+	localparam BLUE_HIGH         = 7'b1101101;
+	localparam PADDING_LOW       = 7'b1101110;
+	localparam PADDING_HIGH      = 7'b1101111;
+
+	localparam IGNORE            = 7'b1111111;
+
+	localparam ETHER_TYPE_IPV6 = 16'h86dd;
+
+	reg  [6:0] state;
+	reg        broadcast;
+	reg [23:0] pixel_addr;
+	reg [16:0] pixel_data;
+
+	wire maybe_broadcast;
+
+	assign maybe_broadcast = broadcast && rxd == 4'hf;
+
+	wire [23:0] base_addr;
+
+	assign base_addr = pixel_addr * 3 >> 1;
+
+	initial begin
+		bus_clk <= 0;
+		bus_data <= 16'b0;
+		bus_addr <= 24'b0;
+		bus_sel <= 2'b0;
+
+		state <= PREAMBLE;
+		broadcast <= 0;
+		pixel_addr <= 24'b0;
+		pixel_data <= 16'b0;
+	end
+
+	always @(posedge rx_clk) begin
+		if (rx_dv && ~rx_er) begin
+			if (state >= DEST_0 && state < ETHER_TYPE_3 || state >= TRAFFIC_CLASS_0 && state < PADDING_HIGH) state <= state + 1;
+			else if (state == ETHER_TYPE_3) state <= TRAFFIC_CLASS_0;
+			else if (state == PADDING_HIGH) state <= IGNORE;
+
+			broadcast <= maybe_broadcast;
+
+			case (state)
+			PREAMBLE: begin
+				if (rxd == 4'hd) begin
+					state <= DEST_0;
+					broadcast <= 1;
+				end
+			end
+			DEST_0: if (rxd != MAC_ADDRESS[43:40] && ~maybe_broadcast) state <= IGNORE;
+			DEST_1: if (rxd != MAC_ADDRESS[47:44] && ~maybe_broadcast) state <= IGNORE;
+			DEST_2: if (rxd != MAC_ADDRESS[35:32] && ~maybe_broadcast) state <= IGNORE;
+			DEST_3: if (rxd != MAC_ADDRESS[39:36] && ~maybe_broadcast) state <= IGNORE;
+			DEST_4: if (rxd != MAC_ADDRESS[27:24] && ~maybe_broadcast) state <= IGNORE;
+			DEST_5: if (rxd != MAC_ADDRESS[31:28] && ~maybe_broadcast) state <= IGNORE;
+			DEST_6: if (rxd != MAC_ADDRESS[19:16] && ~maybe_broadcast) state <= IGNORE;
+			DEST_7: if (rxd != MAC_ADDRESS[23:20] && ~maybe_broadcast) state <= IGNORE;
+			DEST_8: if (rxd != MAC_ADDRESS[11: 8] && ~maybe_broadcast) state <= IGNORE;
+			DEST_9: if (rxd != MAC_ADDRESS[15:12] && ~maybe_broadcast) state <= IGNORE;
+			DEST_A: if (rxd != MAC_ADDRESS[ 3: 0] && ~maybe_broadcast) state <= IGNORE;
+			DEST_B: if (rxd != MAC_ADDRESS[ 7: 4] && ~maybe_broadcast) state <= IGNORE;
+			ETHER_TYPE_0: if (rxd != ETHER_TYPE_IPV6[11: 8]) state <= IGNORE;
+			ETHER_TYPE_1: if (rxd != ETHER_TYPE_IPV6[15:12]) state <= IGNORE;
+			ETHER_TYPE_2: if (rxd != ETHER_TYPE_IPV6[ 3: 0]) state <= IGNORE;
+			ETHER_TYPE_3: if (rxd != ETHER_TYPE_IPV6[ 7: 4]) state <= IGNORE;
+			VERSION: if (rxd != 4'b0110) state <= IGNORE;
+			X_0: pixel_addr[11:8] <= rxd;
+			X_2: pixel_addr[ 3:0] <= rxd;
+			X_3: pixel_addr[ 7:4] <= rxd;
+			Y_2: pixel_addr <= pixel_addr + rxd * SCREEN_WIDTH;
+			Y_3: pixel_addr <= pixel_addr + {rxd, 4'b0} * SCREEN_WIDTH;
+			RED_LOW: begin
+				if (pixel_addr[0]) pixel_data[11:8] <= rxd;
+				else               pixel_data[ 3:0] <= rxd;
+			end
+			RED_HIGH: begin
+				if (pixel_addr[0]) pixel_data[15:12] <= rxd;
+				else               pixel_data[ 7: 4] <= rxd;
+			end
+			GREEN_LOW: begin
+				if (pixel_addr[0]) begin
+					pixel_data[ 3:0] <= rxd;
+				end else begin
+					bus_data <= pixel_data;
+					bus_addr <= base_addr + 1;
+					bus_sel <= 2'b01;
+
+					pixel_data[11:8] <= rxd;
+				end
+			end
+			GREEN_HIGH: begin
+				if (pixel_addr[0]) begin
+					pixel_data[ 7: 4] <= rxd;
+				end else begin
+					bus_clk <= 1;
+
+					pixel_data[15:12] <= rxd;
+				end
+			end
+			BLUE_LOW: begin
+				if (pixel_addr[0]) begin
+					bus_data <= pixel_data;
+					bus_addr <= base_addr + 1;
+					bus_sel <= 2'b11;
+
+					pixel_data[11:8] <= rxd;
+				end else begin
+					bus_clk <= 0;
+
+					pixel_data[ 3:0] <= rxd;
+				end
+			end
+			BLUE_HIGH: begin
+				if (pixel_addr[0]) begin
+					bus_clk <= 1;
+
+					pixel_data[15:12] <= rxd;
+				end else begin
+					pixel_data[ 7: 4] <= rxd;
+				end
+			end
+			PADDING_LOW: begin
+				bus_data <= pixel_data;
+
+				if (pixel_addr[0]) begin
+					bus_clk <= 0;
+					bus_addr <= base_addr;
+					bus_sel <= 2'b10;
+				end else begin
+					bus_addr <= base_addr;
+					bus_sel <= 2'b11;
+				end
+			end
+			PADDING_HIGH: bus_clk <= 1;
+			IGNORE: bus_clk <= 0;
+			endcase
+		end else begin
+			bus_clk <= 0;
+
+			state <= PREAMBLE;
+			pixel_addr <= 24'b0;
+			pixel_data <= 16'b0;
+		end
+	end
+endmodule

pingxelflut_state.txt

@@ -0,0 +1,64 @@
+0000000 PREAMBLE
+0000001 DEST_0
+0000010 DEST_1
+0000011 DEST_2
+0000100 DEST_3
+0000101 DEST_4
+0000110 DEST_5
+0000111 DEST_6
+0001000 DEST_7
+0001001 DEST_8
+0001010 DEST_9
+0001011 DEST_A
+0001100 DEST_B
+0001101 SRC_0
+0001110 SRC_1
+0001111 SRC_2
+0010000 SRC_3
+0010001 SRC_4
+0010010 SRC_5
+0010011 SRC_6
+0010100 SRC_7
+0010101 SRC_8
+0010110 SRC_9
+0010111 SRC_A
+0011000 SRC_B
+0011001 ETHER_TYPE_0
+0011010 ETHER_TYPE_1
+0011011 ETHER_TYPE_2
+0011100 ETHER_TYPE_3
+0100000 TRAFFIC_CLASS_0
+0100001 VERSION
+0100010 FLOW_LABEL_0
+0100011 TRAFFIC_CLASS_1
+0100100 FLOW_LABEL_1
+0100101 FLOW_LABEL_2
+0100110 FLOW_LABEL_3
+0100111 FLOW_LABEL_4
+0101000 PAYLOAD_LENGTH_0
+0101001 PAYLOAD_LENGTH_1
+0101010 PAYLOAD_LENGTH_2
+0101011 PAYLOAD_LENGTH_3
+0101100 NEXT_HEADER_0
+0101101 NEXT_HEADER_1
+0101110 HOP_LIMIT_0
+0101111 HOP_LIMIT_1
+0110000 SRC_ADDR_0
+1010000 DEST_PREFIX_0
+1100000 X_0
+1100001 X_1
+1100010 X_2
+1100011 X_3
+1100100 Y_0
+1100101 Y_1
+1100110 Y_2
+1100111 Y_3
+1101000 RED_LOW
+1101001 RED_HIGH
+1101010 GREEN_LOW
+1101011 GREEN_HIGH
+1101100 BLUE_LOW
+1101101 BLUE_HIGH
+1101110 PADDING_LOW
+1101111 PADDING_HIGH
+1111111 IGNORE

pingxelflut_tb.hex

@@ -0,0 +1,129 @@
+d
+2
+0
+0
+0
+0
+0
+0
+0
+0
+0
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+d
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+f
+f
+f
+f
+f
+f
+f
+f
+0
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+0
+0
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+0
+1
+0
+c
+f
+0
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+3
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+0
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+0
+0

pingxelflut_tb.v

@@ -0,0 +1,42 @@
+`timescale 1 ns / 1 ns
+
+module testbench();
+	reg clk = 0;
+
+	always #20 clk = ~clk;
+
+	reg [3:0] rxd;
+
+	wire        bus_clk;
+	wire [15:0] bus_data;
+	wire [23:0] bus_addr;
+	wire  [1:0] bus_sel;
+
+	pingxelflut eth (
+		.rx_clk  (clk),
+		.rxd     (rxd),
+		.rx_dv   (1'b1),
+		.rx_er   (1'b0),
+
+		.bus_clk (bus_clk),
+		.bus_data(bus_data),
+		.bus_addr(bus_addr),
+		.bus_sel (bus_sel)
+	);
+
+	reg [3:0] test_data [0:128];
+
+	initial begin
+		$dumpfile("pingxelflut_tb.vcd");
+		$dumpvars(0, testbench);
+
+		$readmemh("pingxelflut_tb.hex", test_data);
+
+		rxd <= test_data[0];
+		#10;
+		for (integer i = 1; i < 129; i = i + 1) #40 rxd <= test_data[i];
+
+		$finish;
+	end
+endmodule
+

pixelflut.v

@@ -10,14 +10,30 @@ module pixelflut (
 	output        dvi_de,
 	output        dvi_hs,
 	output        dvi_vs,
+
+	output        eth_mdc,
+	inout         eth_mdio,
+	output        eth_ref_clk,
+	output        eth_rstn,
+	input         eth_rx_clk,
+	input         eth_rx_dv,
+	input   [3:0] eth_rxd,
+	input         eth_rxerr,
+	input         eth_tx_clk,
+	output        eth_tx_en,
+	output  [3:0] eth_txd,
 );
 	reg [31:0] ctr;
-	reg  [2:0] led0_state = 3'b0;
+	reg  [2:0] led0_state;
 
 	assign led0_r = led0_state[0];
 	assign led0_g = led0_state[1];
 	assign led0_b = led0_state[2];
 
+	initial begin
+		led0_state <= 3'b0;
+	end
+
 	always @(posedge sys_clk) begin
 		if (ctr == 32'd50_000_000) begin
 			ctr <= 32'b0;
@@ -48,13 +64,62 @@ module pixelflut (
 		.vs      (dvi_vs),
 	);
 
+	reg [1:0] eth_clk_div;
+
+	assign eth_ref_clk = eth_clk_div[1];
+
+	initial begin
+		eth_clk_div <= 2'b0;
+	end
+
+	always @(posedge sys_clk) begin
+		eth_clk_div <= eth_clk_div + 1;
+	end
+
+	assign eth_rstn  = 1;
+	assign eth_tx_en = 0;
+	assign eth_txd = 4'b0;
+
+	wire eth_mdio_i, eth_mdio_o, eth_mdio_en;
+
+	IOBUF eth_mdio_buf (
+		.I (eth_mdio_o),
+		.IO(eth_mdio),
+		.O (eth_mdio_i),
+		.T (eth_mdio_en),
+	);
+
+	ethernet_smi smi (
+		.clk    (sys_clk),
+		.mdio_i (eth_mdio_i),
+		.mdio_o (eth_mdio_o),
+		.mdio_en(eth_mdio_en),
+		.mdc    (eth_mdc),
+	);
+
+	wire        eth_bus_clk;
+	wire [15:0] eth_bus_data;
+	wire [23:0] eth_bus_addr;
+	wire  [1:0] eth_bus_sel;
+
+	pingxelflut eth (
+		.rx_clk  (eth_rx_clk),
+		.rxd     (eth_rxd),
+		.rx_dv   (eth_rx_dv),
+		.rx_er   (eth_rxerr),
+		.bus_clk (eth_bus_clk),
+		.bus_data(eth_bus_data),
+		.bus_addr(eth_bus_addr),
+		.bus_sel (eth_bus_sel),
+	);
+
 	xc7_bram ram (
 		.out_clk (dvi_bus_clk),
 		.out_data(dvi_bus_data),
 		.out_addr(dvi_bus_addr),
-		.in_clk  (),
+		.in_clk  (eth_bus_clk),
-		.in_data (),
+		.in_data (eth_bus_data),
-		.in_addr (),
+		.in_addr (eth_bus_addr),
-		.in_wren (),
+		.in_wren (eth_bus_sel),
 	);
 endmodule

xc7_bram.v

@@ -10,7 +10,7 @@ module xc7_bram #(
 	input  [23:0] in_addr,
 	input   [1:0] in_wren,
 );
-	wire [31:0] porta_out [NUM_BLOCKS-1:0];
+	wire [31:0] porta_out [0:NUM_BLOCKS-1];
 	wire [15:0] porta_addr, portb_addr;
 
 	assign out_data = porta_out[out_addr[16:11]][15:0];
@@ -30,6 +30,8 @@ module xc7_bram #(
 				.ADDRARDADDR(porta_addr),
 				.CLKARDCLK  (out_clk),
 				.ENARDEN    (1'b1),
+				.DIADI      (32'b0),
+				.WEA        (4'b0),
 				.ADDRBWRADDR(portb_addr),
 				.CLKBWRCLK  (in_clk),
 				.ENBWREN    (in_addr[16:11] == i),