refactor: group DDR3L pins
This commit is contained in:
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7a16c919bc
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c66deb56bc
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@ -218,23 +218,23 @@ set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports eth_txd[
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## DDR3L RAM
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set_property -dict { PACKAGE_PIN K6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_reset]
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set_property -dict { PACKAGE_PIN R5 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_odt]
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set_property -dict { PACKAGE_PIN R2 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a0]
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set_property -dict { PACKAGE_PIN M6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a1]
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set_property -dict { PACKAGE_PIN N4 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a2]
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set_property -dict { PACKAGE_PIN T1 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a3]
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set_property -dict { PACKAGE_PIN N6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a4]
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set_property -dict { PACKAGE_PIN R7 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a5]
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set_property -dict { PACKAGE_PIN V6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a6]
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set_property -dict { PACKAGE_PIN U7 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a7]
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set_property -dict { PACKAGE_PIN R8 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a8]
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set_property -dict { PACKAGE_PIN V7 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a9]
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set_property -dict { PACKAGE_PIN R6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a10]
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set_property -dict { PACKAGE_PIN U6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a11]
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set_property -dict { PACKAGE_PIN T6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a12]
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set_property -dict { PACKAGE_PIN T8 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a13]
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set_property -dict { PACKAGE_PIN R1 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_ba0]
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set_property -dict { PACKAGE_PIN P4 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_ba1]
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set_property -dict { PACKAGE_PIN P2 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_ba2]
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set_property -dict { PACKAGE_PIN R2 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[0]]
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set_property -dict { PACKAGE_PIN M6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[1]]
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set_property -dict { PACKAGE_PIN N4 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[2]]
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set_property -dict { PACKAGE_PIN T1 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[3]]
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set_property -dict { PACKAGE_PIN N6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[4]]
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set_property -dict { PACKAGE_PIN R7 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[5]]
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set_property -dict { PACKAGE_PIN V6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[6]]
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set_property -dict { PACKAGE_PIN U7 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[7]]
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set_property -dict { PACKAGE_PIN R8 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[8]]
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set_property -dict { PACKAGE_PIN V7 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[9]]
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set_property -dict { PACKAGE_PIN R6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[10]]
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set_property -dict { PACKAGE_PIN U6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[11]]
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set_property -dict { PACKAGE_PIN T6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[12]]
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set_property -dict { PACKAGE_PIN T8 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[13]]
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set_property -dict { PACKAGE_PIN R1 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_ba[0]]
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set_property -dict { PACKAGE_PIN P4 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_ba[1]]
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set_property -dict { PACKAGE_PIN P2 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_ba[2]]
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set_property -dict { PACKAGE_PIN U8 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_cs]
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set_property -dict { PACKAGE_PIN P3 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_ras]
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set_property -dict { PACKAGE_PIN M4 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_cas]
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@ -242,24 +242,24 @@ set_property -dict { PACKAGE_PIN P5 IOSTANDARD SSTL135_R SLEW FAST
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set_property -dict { PACKAGE_PIN N5 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_cke0]
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set_property -dict { PACKAGE_PIN U9 IOSTANDARD DIFF_SSTL135_R SLEW FAST } [get_ports ddr3_clk0_p]
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set_property -dict { PACKAGE_PIN V9 IOSTANDARD DIFF_SSTL135_R SLEW FAST } [get_ports ddr3_clk0_n]
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set_property -dict { PACKAGE_PIN L1 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dm0]
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set_property -dict { PACKAGE_PIN U1 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dm1]
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set_property -dict { PACKAGE_PIN K5 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq0]
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set_property -dict { PACKAGE_PIN L3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq1]
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set_property -dict { PACKAGE_PIN K3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq2]
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set_property -dict { PACKAGE_PIN L6 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq3]
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set_property -dict { PACKAGE_PIN M3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq4]
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set_property -dict { PACKAGE_PIN M1 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq5]
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set_property -dict { PACKAGE_PIN L4 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq6]
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set_property -dict { PACKAGE_PIN M2 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq7]
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set_property -dict { PACKAGE_PIN V4 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq8]
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set_property -dict { PACKAGE_PIN T5 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq9]
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set_property -dict { PACKAGE_PIN U4 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq10]
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set_property -dict { PACKAGE_PIN V5 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq11]
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set_property -dict { PACKAGE_PIN V1 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq12]
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set_property -dict { PACKAGE_PIN T3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq13]
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set_property -dict { PACKAGE_PIN U3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq14]
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set_property -dict { PACKAGE_PIN R3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq15]
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set_property -dict { PACKAGE_PIN L1 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dm[0]]
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set_property -dict { PACKAGE_PIN U1 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dm[1]]
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set_property -dict { PACKAGE_PIN K5 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[0]]
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set_property -dict { PACKAGE_PIN L3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[1]]
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set_property -dict { PACKAGE_PIN K3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[2]]
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set_property -dict { PACKAGE_PIN L6 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[3]]
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set_property -dict { PACKAGE_PIN M3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[4]]
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set_property -dict { PACKAGE_PIN M1 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[5]]
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set_property -dict { PACKAGE_PIN L4 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[6]]
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set_property -dict { PACKAGE_PIN M2 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[7]]
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set_property -dict { PACKAGE_PIN V4 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[8]]
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set_property -dict { PACKAGE_PIN T5 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[9]]
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set_property -dict { PACKAGE_PIN U4 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[10]]
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set_property -dict { PACKAGE_PIN V5 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[11]]
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set_property -dict { PACKAGE_PIN V1 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[12]]
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set_property -dict { PACKAGE_PIN T3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[13]]
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set_property -dict { PACKAGE_PIN U3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[14]]
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set_property -dict { PACKAGE_PIN R3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[15]]
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set_property -dict { PACKAGE_PIN N2 IOSTANDARD DIFF_SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dqs0_p]
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set_property -dict { PACKAGE_PIN N1 IOSTANDARD DIFF_SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dqs0_n]
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set_property -dict { PACKAGE_PIN U2 IOSTANDARD DIFF_SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dqs1_p]
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55
ddr3l.v
55
ddr3l.v
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@ -1,51 +1,22 @@
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module ddr3l (
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output reset,
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output odt,
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output a0,
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output a1,
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output a2,
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output a3,
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output a4,
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output a5,
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output a6,
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output a7,
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output a8,
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output a9,
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output a10,
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output a11,
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output a12,
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output a13,
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output ba0,
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output ba1,
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output ba2,
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output [13:0] a,
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output [2:0] ba,
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output cs,
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output ras,
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output cas,
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output we,
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output cke0,
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output clk0_p,
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output clk0_n,
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output dm0,
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output dm1,
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inout dq0,
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inout dq1,
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inout dq2,
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inout dq3,
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inout dq4,
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inout dq5,
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inout dq6,
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inout dq7,
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inout dq8,
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inout dq9,
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inout dq10,
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inout dq11,
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inout dq12,
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inout dq13,
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inout dq14,
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inout dq15,
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inout dqs0_p,
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inout dqs0_n,
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inout dqs1_p,
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inout dqs1_n,
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output cke,
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output clk,
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output [1:0] dm,
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input [15:0] dq_i,
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output [15:0] dq_o,
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output dq_en,
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input [1:0] dqs_i,
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output [1:0] dqs_o,
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output dqs_en,
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);
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endmodule
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230
pixelflut.v
230
pixelflut.v
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@ -7,23 +7,8 @@ module pixelflut (
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output ddr3_reset,
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output ddr3_odt,
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output ddr3_a0,
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output ddr3_a1,
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output ddr3_a2,
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output ddr3_a3,
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output ddr3_a4,
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output ddr3_a5,
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output ddr3_a6,
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output ddr3_a7,
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output ddr3_a8,
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output ddr3_a9,
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output ddr3_a10,
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output ddr3_a11,
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output ddr3_a12,
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output ddr3_a13,
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output ddr3_ba0,
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output ddr3_ba1,
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output ddr3_ba2,
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output [13:0] ddr3_a,
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output [2:0] ddr3_ba,
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output ddr3_cs,
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output ddr3_ras,
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output ddr3_cas,
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@ -31,24 +16,8 @@ module pixelflut (
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output ddr3_cke0,
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output ddr3_clk0_p,
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output ddr3_clk0_n,
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output ddr3_dm0,
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output ddr3_dm1,
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inout ddr3_dq0,
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inout ddr3_dq1,
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inout ddr3_dq2,
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inout ddr3_dq3,
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inout ddr3_dq4,
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inout ddr3_dq5,
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inout ddr3_dq6,
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inout ddr3_dq7,
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inout ddr3_dq8,
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inout ddr3_dq9,
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inout ddr3_dq10,
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inout ddr3_dq11,
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inout ddr3_dq12,
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inout ddr3_dq13,
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inout ddr3_dq14,
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inout ddr3_dq15,
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output [1:0] ddr3_dm,
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inout [15:0] ddr3_dq,
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inout ddr3_dqs0_p,
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inout ddr3_dqs0_n,
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inout ddr3_dqs1_p,
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@ -70,54 +39,161 @@ module pixelflut (
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end
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end
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wire ddr3_clk, ddr3_dq_en, ddr3_dqs_en;
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wire [15:0] ddr3_dq_i, ddr3_dq_o;
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wire [1:0] ddr3_dqs_i, ddr3_dqs_o;
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OBUFDS ddr3_clk0 (
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.I (ddr3_clk),
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.O (ddr3_clk0_p),
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.OB(ddr3_clk0_n),
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);
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IOBUF ddr3_dq0 (
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.I (ddr3_dq_o[0]),
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.IO(ddr3_dq[0]),
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.O (ddr3_dq_i[0]),
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.T (ddr3_dq_en),
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);
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IOBUF ddr3_dq1 (
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.I (ddr3_dq_o[1]),
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.IO(ddr3_dq[1]),
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.O (ddr3_dq_i[1]),
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.T (ddr3_dq_en),
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);
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IOBUF ddr3_dq2 (
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.I (ddr3_dq_o[2]),
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.IO(ddr3_dq[2]),
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.O (ddr3_dq_i[2]),
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.T (ddr3_dq_en),
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);
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IOBUF ddr3_dq3 (
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.I (ddr3_dq_o[3]),
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.IO(ddr3_dq[3]),
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.O (ddr3_dq_i[3]),
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.T (ddr3_dq_en),
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);
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IOBUF ddr3_dq4 (
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.I (ddr3_dq_o[4]),
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.IO(ddr3_dq[4]),
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.O (ddr3_dq_i[4]),
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.T (ddr3_dq_en),
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);
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IOBUF ddr3_dq5 (
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.I (ddr3_dq_o[5]),
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.IO(ddr3_dq[5]),
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.O (ddr3_dq_i[5]),
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.T (ddr3_dq_en),
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);
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IOBUF ddr3_dq6 (
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.I (ddr3_dq_o[6]),
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.IO(ddr3_dq[6]),
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.O (ddr3_dq_i[6]),
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.T (ddr3_dq_en),
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);
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IOBUF ddr3_dq7 (
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.I (ddr3_dq_o[7]),
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.IO(ddr3_dq[7]),
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.O (ddr3_dq_i[7]),
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.T (ddr3_dq_en),
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);
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IOBUF ddr3_dq8 (
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.I (ddr3_dq_o[8]),
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.IO(ddr3_dq[8]),
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.O (ddr3_dq_i[8]),
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.T (ddr3_dq_en),
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);
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IOBUF ddr3_dq9 (
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.I (ddr3_dq_o[9]),
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.IO(ddr3_dq[9]),
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.O (ddr3_dq_i[9]),
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.T (ddr3_dq_en),
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);
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IOBUF ddr3_dq10 (
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.I (ddr3_dq_o[10]),
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.IO(ddr3_dq[10]),
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.O (ddr3_dq_i[10]),
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.T (ddr3_dq_en),
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);
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IOBUF ddr3_dq11 (
|
||||
.I (ddr3_dq_o[11]),
|
||||
.IO(ddr3_dq[11]),
|
||||
.O (ddr3_dq_i[11]),
|
||||
.T (ddr3_dq_en),
|
||||
);
|
||||
|
||||
IOBUF ddr3_dq12 (
|
||||
.I (ddr3_dq_o[12]),
|
||||
.IO(ddr3_dq[12]),
|
||||
.O (ddr3_dq_i[12]),
|
||||
.T (ddr3_dq_en),
|
||||
);
|
||||
|
||||
IOBUF ddr3_dq13 (
|
||||
.I (ddr3_dq_o[13]),
|
||||
.IO(ddr3_dq[13]),
|
||||
.O (ddr3_dq_i[13]),
|
||||
.T (ddr3_dq_en),
|
||||
);
|
||||
|
||||
IOBUF ddr3_dq14 (
|
||||
.I (ddr3_dq_o[14]),
|
||||
.IO(ddr3_dq[14]),
|
||||
.O (ddr3_dq_i[14]),
|
||||
.T (ddr3_dq_en),
|
||||
);
|
||||
|
||||
IOBUF ddr3_dq15 (
|
||||
.I (ddr3_dq_o[15]),
|
||||
.IO(ddr3_dq[15]),
|
||||
.O (ddr3_dq_i[15]),
|
||||
.T (ddr3_dq_en),
|
||||
);
|
||||
|
||||
IOBUFDS ddr3_dqs0 (
|
||||
.I (ddr3_dqs_o[0]),
|
||||
.IO (ddr3_dqs0_p),
|
||||
.IOB(ddr3_dqs0_n),
|
||||
.O (ddr3_dqs_i[0]),
|
||||
.T (ddr3_dqs_en),
|
||||
);
|
||||
|
||||
IOBUFDS ddr3_dqs1 (
|
||||
.I (ddr3_dqs_o[1]),
|
||||
.IO (ddr3_dqs1_p),
|
||||
.IOB(ddr3_dqs1_n),
|
||||
.O (ddr3_dqs_i[1]),
|
||||
.T (ddr3_dqs_en),
|
||||
);
|
||||
|
||||
ddr3l ram (
|
||||
.reset (ddr3_reset),
|
||||
.odt (ddr3_odt),
|
||||
.a0 (ddr3_a0),
|
||||
.a1 (ddr3_a1),
|
||||
.a2 (ddr3_a2),
|
||||
.a3 (ddr3_a3),
|
||||
.a4 (ddr3_a4),
|
||||
.a5 (ddr3_a5),
|
||||
.a6 (ddr3_a6),
|
||||
.a7 (ddr3_a7),
|
||||
.a8 (ddr3_a8),
|
||||
.a9 (ddr3_a9),
|
||||
.a10 (ddr3_a10),
|
||||
.a11 (ddr3_a11),
|
||||
.a12 (ddr3_a12),
|
||||
.a13 (ddr3_a13),
|
||||
.ba0 (ddr3_ba0),
|
||||
.ba1 (ddr3_ba1),
|
||||
.ba2 (ddr3_ba2),
|
||||
.a (ddr3_a),
|
||||
.ba (ddr3_ba),
|
||||
.cs (ddr3_cs),
|
||||
.ras (ddr3_ras),
|
||||
.cas (ddr3_cas),
|
||||
.we (ddr3_we),
|
||||
.cke0 (ddr3_cke0),
|
||||
.clk0_p (ddr3_clk0_p),
|
||||
.clk0_n (ddr3_clk0_n),
|
||||
.dm0 (ddr3_dm0),
|
||||
.dm1 (ddr3_dm1),
|
||||
.dq0 (ddr3_dq0),
|
||||
.dq1 (ddr3_dq1),
|
||||
.dq2 (ddr3_dq2),
|
||||
.dq3 (ddr3_dq3),
|
||||
.dq4 (ddr3_dq4),
|
||||
.dq5 (ddr3_dq5),
|
||||
.dq6 (ddr3_dq6),
|
||||
.dq7 (ddr3_dq7),
|
||||
.dq8 (ddr3_dq8),
|
||||
.dq9 (ddr3_dq9),
|
||||
.dq10 (ddr3_dq10),
|
||||
.dq11 (ddr3_dq11),
|
||||
.dq12 (ddr3_dq12),
|
||||
.dq13 (ddr3_dq13),
|
||||
.dq14 (ddr3_dq14),
|
||||
.dq15 (ddr3_dq15),
|
||||
.dqs0_p (ddr3_dqs0_p),
|
||||
.dqs0_n (ddr3_dqs0_n),
|
||||
.dqs1_p (ddr3_dqs1_p),
|
||||
.dqs1_n (ddr3_dqs1_n)
|
||||
.cke (ddr3_cke0),
|
||||
.clk (ddr3_clk),
|
||||
.dm (ddr3_dm),
|
||||
.dq_i (ddr3_dq_i),
|
||||
.dq_o (ddr3_dq_o),
|
||||
.dq_en (ddr3_dq_en),
|
||||
.dqs_i (ddr3_dqs_i),
|
||||
.dqs_o (ddr3_dqs_o),
|
||||
.dqs_en(ddr3_dqs_en),
|
||||
);
|
||||
endmodule
|
||||
|
|
|
|||
Loading…
Reference in New Issue