From c66deb56bc2c4360d69d8adc46778c5d8fbdd4e9 Mon Sep 17 00:00:00 2001 From: Luca Date: Fri, 18 Oct 2024 23:45:34 +0200 Subject: [PATCH] refactor: group DDR3L pins --- arty_a7_35t.xdc | 70 ++++++------ ddr3l.v | 67 ++++-------- pixelflut.v | 276 ++++++++++++++++++++++++++++++------------------ 3 files changed, 230 insertions(+), 183 deletions(-) diff --git a/arty_a7_35t.xdc b/arty_a7_35t.xdc index bb83ab2..b4e5ff4 100644 --- a/arty_a7_35t.xdc +++ b/arty_a7_35t.xdc @@ -218,23 +218,23 @@ set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports eth_txd[ ## DDR3L RAM set_property -dict { PACKAGE_PIN K6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_reset] set_property -dict { PACKAGE_PIN R5 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_odt] -set_property -dict { PACKAGE_PIN R2 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a0] -set_property -dict { PACKAGE_PIN M6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a1] -set_property -dict { PACKAGE_PIN N4 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a2] -set_property -dict { PACKAGE_PIN T1 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a3] -set_property -dict { PACKAGE_PIN N6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a4] -set_property -dict { PACKAGE_PIN R7 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a5] -set_property -dict { PACKAGE_PIN V6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a6] -set_property -dict { PACKAGE_PIN U7 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a7] -set_property -dict { PACKAGE_PIN R8 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a8] -set_property -dict { PACKAGE_PIN V7 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a9] -set_property -dict { PACKAGE_PIN R6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a10] -set_property -dict { PACKAGE_PIN U6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a11] -set_property -dict { PACKAGE_PIN T6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a12] -set_property -dict { PACKAGE_PIN T8 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a13] -set_property -dict { PACKAGE_PIN R1 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_ba0] -set_property -dict { PACKAGE_PIN P4 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_ba1] -set_property -dict { PACKAGE_PIN P2 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_ba2] +set_property -dict { PACKAGE_PIN R2 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[0]] +set_property -dict { PACKAGE_PIN M6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[1]] +set_property -dict { PACKAGE_PIN N4 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[2]] +set_property -dict { PACKAGE_PIN T1 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[3]] +set_property -dict { PACKAGE_PIN N6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[4]] +set_property -dict { PACKAGE_PIN R7 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[5]] +set_property -dict { PACKAGE_PIN V6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[6]] +set_property -dict { PACKAGE_PIN U7 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[7]] +set_property -dict { PACKAGE_PIN R8 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[8]] +set_property -dict { PACKAGE_PIN V7 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[9]] +set_property -dict { PACKAGE_PIN R6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[10]] +set_property -dict { PACKAGE_PIN U6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[11]] +set_property -dict { PACKAGE_PIN T6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[12]] +set_property -dict { PACKAGE_PIN T8 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[13]] +set_property -dict { PACKAGE_PIN R1 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_ba[0]] +set_property -dict { PACKAGE_PIN P4 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_ba[1]] +set_property -dict { PACKAGE_PIN P2 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_ba[2]] set_property -dict { PACKAGE_PIN U8 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_cs] set_property -dict { PACKAGE_PIN P3 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_ras] set_property -dict { PACKAGE_PIN M4 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_cas] @@ -242,24 +242,24 @@ set_property -dict { PACKAGE_PIN P5 IOSTANDARD SSTL135_R SLEW FAST set_property -dict { PACKAGE_PIN N5 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_cke0] set_property -dict { PACKAGE_PIN U9 IOSTANDARD DIFF_SSTL135_R SLEW FAST } [get_ports ddr3_clk0_p] set_property -dict { PACKAGE_PIN V9 IOSTANDARD DIFF_SSTL135_R SLEW FAST } [get_ports ddr3_clk0_n] -set_property -dict { PACKAGE_PIN L1 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dm0] -set_property -dict { PACKAGE_PIN U1 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dm1] -set_property -dict { PACKAGE_PIN K5 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq0] -set_property -dict { PACKAGE_PIN L3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq1] -set_property -dict { PACKAGE_PIN K3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq2] -set_property -dict { PACKAGE_PIN L6 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq3] -set_property -dict { PACKAGE_PIN M3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq4] -set_property -dict { PACKAGE_PIN M1 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq5] -set_property -dict { PACKAGE_PIN L4 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq6] -set_property -dict { PACKAGE_PIN M2 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq7] -set_property -dict { PACKAGE_PIN V4 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq8] -set_property -dict { PACKAGE_PIN T5 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq9] -set_property -dict { PACKAGE_PIN U4 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq10] -set_property -dict { PACKAGE_PIN V5 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq11] -set_property -dict { PACKAGE_PIN V1 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq12] -set_property -dict { PACKAGE_PIN T3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq13] -set_property -dict { PACKAGE_PIN U3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq14] -set_property -dict { PACKAGE_PIN R3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq15] +set_property -dict { PACKAGE_PIN L1 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dm[0]] +set_property -dict { PACKAGE_PIN U1 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dm[1]] +set_property -dict { PACKAGE_PIN K5 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[0]] +set_property -dict { PACKAGE_PIN L3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[1]] +set_property -dict { PACKAGE_PIN K3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[2]] +set_property -dict { PACKAGE_PIN L6 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[3]] +set_property -dict { PACKAGE_PIN M3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[4]] +set_property -dict { PACKAGE_PIN M1 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[5]] +set_property -dict { PACKAGE_PIN L4 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[6]] +set_property -dict { PACKAGE_PIN M2 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[7]] +set_property -dict { PACKAGE_PIN V4 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[8]] +set_property -dict { PACKAGE_PIN T5 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[9]] +set_property -dict { PACKAGE_PIN U4 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[10]] +set_property -dict { PACKAGE_PIN V5 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[11]] +set_property -dict { PACKAGE_PIN V1 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[12]] +set_property -dict { PACKAGE_PIN T3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[13]] +set_property -dict { PACKAGE_PIN U3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[14]] +set_property -dict { PACKAGE_PIN R3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[15]] set_property -dict { PACKAGE_PIN N2 IOSTANDARD DIFF_SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dqs0_p] set_property -dict { PACKAGE_PIN N1 IOSTANDARD DIFF_SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dqs0_n] set_property -dict { PACKAGE_PIN U2 IOSTANDARD DIFF_SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dqs1_p] diff --git a/ddr3l.v b/ddr3l.v index 75e5f89..c24f58e 100644 --- a/ddr3l.v +++ b/ddr3l.v @@ -1,51 +1,22 @@ module ddr3l ( - output reset, - output odt, - output a0, - output a1, - output a2, - output a3, - output a4, - output a5, - output a6, - output a7, - output a8, - output a9, - output a10, - output a11, - output a12, - output a13, - output ba0, - output ba1, - output ba2, - output cs, - output ras, - output cas, - output we, - output cke0, - output clk0_p, - output clk0_n, - output dm0, - output dm1, - inout dq0, - inout dq1, - inout dq2, - inout dq3, - inout dq4, - inout dq5, - inout dq6, - inout dq7, - inout dq8, - inout dq9, - inout dq10, - inout dq11, - inout dq12, - inout dq13, - inout dq14, - inout dq15, - inout dqs0_p, - inout dqs0_n, - inout dqs1_p, - inout dqs1_n, + output reset, + output odt, + output [13:0] a, + output [2:0] ba, + output cs, + output ras, + output cas, + output we, + output cke, + output clk, + output [1:0] dm, + + input [15:0] dq_i, + output [15:0] dq_o, + output dq_en, + + input [1:0] dqs_i, + output [1:0] dqs_o, + output dqs_en, ); endmodule diff --git a/pixelflut.v b/pixelflut.v index 940c4dd..1d8b712 100644 --- a/pixelflut.v +++ b/pixelflut.v @@ -1,58 +1,27 @@ module pixelflut ( - input sys_clk, + input sys_clk, - output led0_r, - output led0_g, - output led0_b, + output led0_r, + output led0_g, + output led0_b, - output ddr3_reset, - output ddr3_odt, - output ddr3_a0, - output ddr3_a1, - output ddr3_a2, - output ddr3_a3, - output ddr3_a4, - output ddr3_a5, - output ddr3_a6, - output ddr3_a7, - output ddr3_a8, - output ddr3_a9, - output ddr3_a10, - output ddr3_a11, - output ddr3_a12, - output ddr3_a13, - output ddr3_ba0, - output ddr3_ba1, - output ddr3_ba2, - output ddr3_cs, - output ddr3_ras, - output ddr3_cas, - output ddr3_we, - output ddr3_cke0, - output ddr3_clk0_p, - output ddr3_clk0_n, - output ddr3_dm0, - output ddr3_dm1, - inout ddr3_dq0, - inout ddr3_dq1, - inout ddr3_dq2, - inout ddr3_dq3, - inout ddr3_dq4, - inout ddr3_dq5, - inout ddr3_dq6, - inout ddr3_dq7, - inout ddr3_dq8, - inout ddr3_dq9, - inout ddr3_dq10, - inout ddr3_dq11, - inout ddr3_dq12, - inout ddr3_dq13, - inout ddr3_dq14, - inout ddr3_dq15, - inout ddr3_dqs0_p, - inout ddr3_dqs0_n, - inout ddr3_dqs1_p, - inout ddr3_dqs1_n, + output ddr3_reset, + output ddr3_odt, + output [13:0] ddr3_a, + output [2:0] ddr3_ba, + output ddr3_cs, + output ddr3_ras, + output ddr3_cas, + output ddr3_we, + output ddr3_cke0, + output ddr3_clk0_p, + output ddr3_clk0_n, + output [1:0] ddr3_dm, + inout [15:0] ddr3_dq, + inout ddr3_dqs0_p, + inout ddr3_dqs0_n, + inout ddr3_dqs1_p, + inout ddr3_dqs1_n, ); reg [31:0] ctr; reg [2:0] led0_state = 3'b0; @@ -70,54 +39,161 @@ module pixelflut ( end end + wire ddr3_clk, ddr3_dq_en, ddr3_dqs_en; + wire [15:0] ddr3_dq_i, ddr3_dq_o; + wire [1:0] ddr3_dqs_i, ddr3_dqs_o; + + OBUFDS ddr3_clk0 ( + .I (ddr3_clk), + .O (ddr3_clk0_p), + .OB(ddr3_clk0_n), + ); + + IOBUF ddr3_dq0 ( + .I (ddr3_dq_o[0]), + .IO(ddr3_dq[0]), + .O (ddr3_dq_i[0]), + .T (ddr3_dq_en), + ); + + IOBUF ddr3_dq1 ( + .I (ddr3_dq_o[1]), + .IO(ddr3_dq[1]), + .O (ddr3_dq_i[1]), + .T (ddr3_dq_en), + ); + + IOBUF ddr3_dq2 ( + .I (ddr3_dq_o[2]), + .IO(ddr3_dq[2]), + .O (ddr3_dq_i[2]), + .T (ddr3_dq_en), + ); + + IOBUF ddr3_dq3 ( + .I (ddr3_dq_o[3]), + .IO(ddr3_dq[3]), + .O (ddr3_dq_i[3]), + .T (ddr3_dq_en), + ); + + IOBUF ddr3_dq4 ( + .I (ddr3_dq_o[4]), + .IO(ddr3_dq[4]), + .O (ddr3_dq_i[4]), + .T (ddr3_dq_en), + ); + + IOBUF ddr3_dq5 ( + .I (ddr3_dq_o[5]), + .IO(ddr3_dq[5]), + .O (ddr3_dq_i[5]), + .T (ddr3_dq_en), + ); + + IOBUF ddr3_dq6 ( + .I (ddr3_dq_o[6]), + .IO(ddr3_dq[6]), + .O (ddr3_dq_i[6]), + .T (ddr3_dq_en), + ); + + IOBUF ddr3_dq7 ( + .I (ddr3_dq_o[7]), + .IO(ddr3_dq[7]), + .O (ddr3_dq_i[7]), + .T (ddr3_dq_en), + ); + + IOBUF ddr3_dq8 ( + .I (ddr3_dq_o[8]), + .IO(ddr3_dq[8]), + .O (ddr3_dq_i[8]), + .T (ddr3_dq_en), + ); + + IOBUF ddr3_dq9 ( + .I (ddr3_dq_o[9]), + .IO(ddr3_dq[9]), + .O (ddr3_dq_i[9]), + .T (ddr3_dq_en), + ); + + IOBUF ddr3_dq10 ( + .I (ddr3_dq_o[10]), + .IO(ddr3_dq[10]), + .O (ddr3_dq_i[10]), + .T (ddr3_dq_en), + ); + + IOBUF ddr3_dq11 ( + .I (ddr3_dq_o[11]), + .IO(ddr3_dq[11]), + .O (ddr3_dq_i[11]), + .T (ddr3_dq_en), + ); + + IOBUF ddr3_dq12 ( + .I (ddr3_dq_o[12]), + .IO(ddr3_dq[12]), + .O (ddr3_dq_i[12]), + .T (ddr3_dq_en), + ); + + IOBUF ddr3_dq13 ( + .I (ddr3_dq_o[13]), + .IO(ddr3_dq[13]), + .O (ddr3_dq_i[13]), + .T (ddr3_dq_en), + ); + + IOBUF ddr3_dq14 ( + .I (ddr3_dq_o[14]), + .IO(ddr3_dq[14]), + .O (ddr3_dq_i[14]), + .T (ddr3_dq_en), + ); + + IOBUF ddr3_dq15 ( + .I (ddr3_dq_o[15]), + .IO(ddr3_dq[15]), + .O (ddr3_dq_i[15]), + .T (ddr3_dq_en), + ); + + IOBUFDS ddr3_dqs0 ( + .I (ddr3_dqs_o[0]), + .IO (ddr3_dqs0_p), + .IOB(ddr3_dqs0_n), + .O (ddr3_dqs_i[0]), + .T (ddr3_dqs_en), + ); + + IOBUFDS ddr3_dqs1 ( + .I (ddr3_dqs_o[1]), + .IO (ddr3_dqs1_p), + .IOB(ddr3_dqs1_n), + .O (ddr3_dqs_i[1]), + .T (ddr3_dqs_en), + ); + ddr3l ram ( - .reset (ddr3_reset), - .odt (ddr3_odt), - .a0 (ddr3_a0), - .a1 (ddr3_a1), - .a2 (ddr3_a2), - .a3 (ddr3_a3), - .a4 (ddr3_a4), - .a5 (ddr3_a5), - .a6 (ddr3_a6), - .a7 (ddr3_a7), - .a8 (ddr3_a8), - .a9 (ddr3_a9), - .a10 (ddr3_a10), - .a11 (ddr3_a11), - .a12 (ddr3_a12), - .a13 (ddr3_a13), - .ba0 (ddr3_ba0), - .ba1 (ddr3_ba1), - .ba2 (ddr3_ba2), - .cs (ddr3_cs), - .ras (ddr3_ras), - .cas (ddr3_cas), - .we (ddr3_we), - .cke0 (ddr3_cke0), - .clk0_p (ddr3_clk0_p), - .clk0_n (ddr3_clk0_n), - .dm0 (ddr3_dm0), - .dm1 (ddr3_dm1), - .dq0 (ddr3_dq0), - .dq1 (ddr3_dq1), - .dq2 (ddr3_dq2), - .dq3 (ddr3_dq3), - .dq4 (ddr3_dq4), - .dq5 (ddr3_dq5), - .dq6 (ddr3_dq6), - .dq7 (ddr3_dq7), - .dq8 (ddr3_dq8), - .dq9 (ddr3_dq9), - .dq10 (ddr3_dq10), - .dq11 (ddr3_dq11), - .dq12 (ddr3_dq12), - .dq13 (ddr3_dq13), - .dq14 (ddr3_dq14), - .dq15 (ddr3_dq15), - .dqs0_p (ddr3_dqs0_p), - .dqs0_n (ddr3_dqs0_n), - .dqs1_p (ddr3_dqs1_p), - .dqs1_n (ddr3_dqs1_n) + .reset (ddr3_reset), + .odt (ddr3_odt), + .a (ddr3_a), + .ba (ddr3_ba), + .cs (ddr3_cs), + .ras (ddr3_ras), + .cas (ddr3_cas), + .we (ddr3_we), + .cke (ddr3_cke0), + .clk (ddr3_clk), + .dm (ddr3_dm), + .dq_i (ddr3_dq_i), + .dq_o (ddr3_dq_o), + .dq_en (ddr3_dq_en), + .dqs_i (ddr3_dqs_i), + .dqs_o (ddr3_dqs_o), + .dqs_en(ddr3_dqs_en), ); endmodule