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refactor: group DDR3L pins

This commit is contained in:
Luca 2024-10-18 23:45:34 +02:00
parent 7a16c919bc
commit c66deb56bc
3 changed files with 230 additions and 183 deletions
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70
arty_a7_35t.xdc
View File

@ -218,23 +218,23 @@ set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports eth_txd[
## DDR3L RAM ## DDR3L RAM
set_property -dict { PACKAGE_PIN K6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_reset] set_property -dict { PACKAGE_PIN K6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_reset]
set_property -dict { PACKAGE_PIN R5 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_odt] set_property -dict { PACKAGE_PIN R5 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_odt]
set_property -dict { PACKAGE_PIN R2 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a0] set_property -dict { PACKAGE_PIN R2 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[0]]
set_property -dict { PACKAGE_PIN M6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a1] set_property -dict { PACKAGE_PIN M6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[1]]
set_property -dict { PACKAGE_PIN N4 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a2] set_property -dict { PACKAGE_PIN N4 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[2]]
set_property -dict { PACKAGE_PIN T1 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a3] set_property -dict { PACKAGE_PIN T1 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[3]]
set_property -dict { PACKAGE_PIN N6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a4] set_property -dict { PACKAGE_PIN N6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[4]]
set_property -dict { PACKAGE_PIN R7 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a5] set_property -dict { PACKAGE_PIN R7 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[5]]
set_property -dict { PACKAGE_PIN V6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a6] set_property -dict { PACKAGE_PIN V6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[6]]
set_property -dict { PACKAGE_PIN U7 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a7] set_property -dict { PACKAGE_PIN U7 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[7]]
set_property -dict { PACKAGE_PIN R8 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a8] set_property -dict { PACKAGE_PIN R8 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[8]]
set_property -dict { PACKAGE_PIN V7 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a9] set_property -dict { PACKAGE_PIN V7 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[9]]
set_property -dict { PACKAGE_PIN R6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a10] set_property -dict { PACKAGE_PIN R6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[10]]
set_property -dict { PACKAGE_PIN U6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a11] set_property -dict { PACKAGE_PIN U6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[11]]
set_property -dict { PACKAGE_PIN T6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a12] set_property -dict { PACKAGE_PIN T6 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[12]]
set_property -dict { PACKAGE_PIN T8 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a13] set_property -dict { PACKAGE_PIN T8 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_a[13]]
set_property -dict { PACKAGE_PIN R1 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_ba0] set_property -dict { PACKAGE_PIN R1 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_ba[0]]
set_property -dict { PACKAGE_PIN P4 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_ba1] set_property -dict { PACKAGE_PIN P4 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_ba[1]]
set_property -dict { PACKAGE_PIN P2 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_ba2] set_property -dict { PACKAGE_PIN P2 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_ba[2]]
set_property -dict { PACKAGE_PIN U8 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_cs] set_property -dict { PACKAGE_PIN U8 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_cs]
set_property -dict { PACKAGE_PIN P3 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_ras] set_property -dict { PACKAGE_PIN P3 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_ras]
set_property -dict { PACKAGE_PIN M4 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_cas] set_property -dict { PACKAGE_PIN M4 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_cas]
@ -242,24 +242,24 @@ set_property -dict { PACKAGE_PIN P5 IOSTANDARD SSTL135_R SLEW FAST
set_property -dict { PACKAGE_PIN N5 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_cke0] set_property -dict { PACKAGE_PIN N5 IOSTANDARD SSTL135_R SLEW FAST } [get_ports ddr3_cke0]
set_property -dict { PACKAGE_PIN U9 IOSTANDARD DIFF_SSTL135_R SLEW FAST } [get_ports ddr3_clk0_p] set_property -dict { PACKAGE_PIN U9 IOSTANDARD DIFF_SSTL135_R SLEW FAST } [get_ports ddr3_clk0_p]
set_property -dict { PACKAGE_PIN V9 IOSTANDARD DIFF_SSTL135_R SLEW FAST } [get_ports ddr3_clk0_n] set_property -dict { PACKAGE_PIN V9 IOSTANDARD DIFF_SSTL135_R SLEW FAST } [get_ports ddr3_clk0_n]
set_property -dict { PACKAGE_PIN L1 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dm0] set_property -dict { PACKAGE_PIN L1 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dm[0]]
set_property -dict { PACKAGE_PIN U1 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dm1] set_property -dict { PACKAGE_PIN U1 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dm[1]]
set_property -dict { PACKAGE_PIN K5 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq0] set_property -dict { PACKAGE_PIN K5 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[0]]
set_property -dict { PACKAGE_PIN L3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq1] set_property -dict { PACKAGE_PIN L3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[1]]
set_property -dict { PACKAGE_PIN K3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq2] set_property -dict { PACKAGE_PIN K3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[2]]
set_property -dict { PACKAGE_PIN L6 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq3] set_property -dict { PACKAGE_PIN L6 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[3]]
set_property -dict { PACKAGE_PIN M3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq4] set_property -dict { PACKAGE_PIN M3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[4]]
set_property -dict { PACKAGE_PIN M1 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq5] set_property -dict { PACKAGE_PIN M1 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[5]]
set_property -dict { PACKAGE_PIN L4 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq6] set_property -dict { PACKAGE_PIN L4 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[6]]
set_property -dict { PACKAGE_PIN M2 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq7] set_property -dict { PACKAGE_PIN M2 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[7]]
set_property -dict { PACKAGE_PIN V4 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq8] set_property -dict { PACKAGE_PIN V4 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[8]]
set_property -dict { PACKAGE_PIN T5 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq9] set_property -dict { PACKAGE_PIN T5 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[9]]
set_property -dict { PACKAGE_PIN U4 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq10] set_property -dict { PACKAGE_PIN U4 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[10]]
set_property -dict { PACKAGE_PIN V5 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq11] set_property -dict { PACKAGE_PIN V5 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[11]]
set_property -dict { PACKAGE_PIN V1 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq12] set_property -dict { PACKAGE_PIN V1 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[12]]
set_property -dict { PACKAGE_PIN T3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq13] set_property -dict { PACKAGE_PIN T3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[13]]
set_property -dict { PACKAGE_PIN U3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq14] set_property -dict { PACKAGE_PIN U3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[14]]
set_property -dict { PACKAGE_PIN R3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq15] set_property -dict { PACKAGE_PIN R3 IOSTANDARD SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dq[15]]
set_property -dict { PACKAGE_PIN N2 IOSTANDARD DIFF_SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dqs0_p] set_property -dict { PACKAGE_PIN N2 IOSTANDARD DIFF_SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dqs0_p]
set_property -dict { PACKAGE_PIN N1 IOSTANDARD DIFF_SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dqs0_n] set_property -dict { PACKAGE_PIN N1 IOSTANDARD DIFF_SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dqs0_n]
set_property -dict { PACKAGE_PIN U2 IOSTANDARD DIFF_SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dqs1_p] set_property -dict { PACKAGE_PIN U2 IOSTANDARD DIFF_SSTL135_R SLEW FAST IN_TERM UNTUNED_SPLIT_50 } [get_ports ddr3_dqs1_p]

67
ddr3l.v
View File

@ -1,51 +1,22 @@
module ddr3l ( module ddr3l (
output reset, output reset,
output odt, output odt,
output a0, output [13:0] a,
output a1, output [2:0] ba,
output a2, output cs,
output a3, output ras,
output a4, output cas,
output a5, output we,
output a6, output cke,
output a7, output clk,
output a8, output [1:0] dm,
output a9,
output a10, input [15:0] dq_i,
output a11, output [15:0] dq_o,
output a12, output dq_en,
output a13,
output ba0, input [1:0] dqs_i,
output ba1, output [1:0] dqs_o,
output ba2, output dqs_en,
output cs,
output ras,
output cas,
output we,
output cke0,
output clk0_p,
output clk0_n,
output dm0,
output dm1,
inout dq0,
inout dq1,
inout dq2,
inout dq3,
inout dq4,
inout dq5,
inout dq6,
inout dq7,
inout dq8,
inout dq9,
inout dq10,
inout dq11,
inout dq12,
inout dq13,
inout dq14,
inout dq15,
inout dqs0_p,
inout dqs0_n,
inout dqs1_p,
inout dqs1_n,
); );
endmodule endmodule

276
pixelflut.v
View File

@ -1,58 +1,27 @@
module pixelflut ( module pixelflut (
input sys_clk, input sys_clk,
output led0_r, output led0_r,
output led0_g, output led0_g,
output led0_b, output led0_b,
output ddr3_reset, output ddr3_reset,
output ddr3_odt, output ddr3_odt,
output ddr3_a0, output [13:0] ddr3_a,
output ddr3_a1, output [2:0] ddr3_ba,
output ddr3_a2, output ddr3_cs,
output ddr3_a3, output ddr3_ras,
output ddr3_a4, output ddr3_cas,
output ddr3_a5, output ddr3_we,
output ddr3_a6, output ddr3_cke0,
output ddr3_a7, output ddr3_clk0_p,
output ddr3_a8, output ddr3_clk0_n,
output ddr3_a9, output [1:0] ddr3_dm,
output ddr3_a10, inout [15:0] ddr3_dq,
output ddr3_a11, inout ddr3_dqs0_p,
output ddr3_a12, inout ddr3_dqs0_n,
output ddr3_a13, inout ddr3_dqs1_p,
output ddr3_ba0, inout ddr3_dqs1_n,
output ddr3_ba1,
output ddr3_ba2,
output ddr3_cs,
output ddr3_ras,
output ddr3_cas,
output ddr3_we,
output ddr3_cke0,
output ddr3_clk0_p,
output ddr3_clk0_n,
output ddr3_dm0,
output ddr3_dm1,
inout ddr3_dq0,
inout ddr3_dq1,
inout ddr3_dq2,
inout ddr3_dq3,
inout ddr3_dq4,
inout ddr3_dq5,
inout ddr3_dq6,
inout ddr3_dq7,
inout ddr3_dq8,
inout ddr3_dq9,
inout ddr3_dq10,
inout ddr3_dq11,
inout ddr3_dq12,
inout ddr3_dq13,
inout ddr3_dq14,
inout ddr3_dq15,
inout ddr3_dqs0_p,
inout ddr3_dqs0_n,
inout ddr3_dqs1_p,
inout ddr3_dqs1_n,
); );
reg [31:0] ctr; reg [31:0] ctr;
reg [2:0] led0_state = 3'b0; reg [2:0] led0_state = 3'b0;
@ -70,54 +39,161 @@ module pixelflut (
end end
end end
wire ddr3_clk, ddr3_dq_en, ddr3_dqs_en;
wire [15:0] ddr3_dq_i, ddr3_dq_o;
wire [1:0] ddr3_dqs_i, ddr3_dqs_o;
OBUFDS ddr3_clk0 (
.I (ddr3_clk),
.O (ddr3_clk0_p),
.OB(ddr3_clk0_n),
);
IOBUF ddr3_dq0 (
.I (ddr3_dq_o[0]),
.IO(ddr3_dq[0]),
.O (ddr3_dq_i[0]),
.T (ddr3_dq_en),
);
IOBUF ddr3_dq1 (
.I (ddr3_dq_o[1]),
.IO(ddr3_dq[1]),
.O (ddr3_dq_i[1]),
.T (ddr3_dq_en),
);
IOBUF ddr3_dq2 (
.I (ddr3_dq_o[2]),
.IO(ddr3_dq[2]),
.O (ddr3_dq_i[2]),
.T (ddr3_dq_en),
);
IOBUF ddr3_dq3 (
.I (ddr3_dq_o[3]),
.IO(ddr3_dq[3]),
.O (ddr3_dq_i[3]),
.T (ddr3_dq_en),
);
IOBUF ddr3_dq4 (
.I (ddr3_dq_o[4]),
.IO(ddr3_dq[4]),
.O (ddr3_dq_i[4]),
.T (ddr3_dq_en),
);
IOBUF ddr3_dq5 (
.I (ddr3_dq_o[5]),
.IO(ddr3_dq[5]),
.O (ddr3_dq_i[5]),
.T (ddr3_dq_en),
);
IOBUF ddr3_dq6 (
.I (ddr3_dq_o[6]),
.IO(ddr3_dq[6]),
.O (ddr3_dq_i[6]),
.T (ddr3_dq_en),
);
IOBUF ddr3_dq7 (
.I (ddr3_dq_o[7]),
.IO(ddr3_dq[7]),
.O (ddr3_dq_i[7]),
.T (ddr3_dq_en),
);
IOBUF ddr3_dq8 (
.I (ddr3_dq_o[8]),
.IO(ddr3_dq[8]),
.O (ddr3_dq_i[8]),
.T (ddr3_dq_en),
);
IOBUF ddr3_dq9 (
.I (ddr3_dq_o[9]),
.IO(ddr3_dq[9]),
.O (ddr3_dq_i[9]),
.T (ddr3_dq_en),
);
IOBUF ddr3_dq10 (
.I (ddr3_dq_o[10]),
.IO(ddr3_dq[10]),
.O (ddr3_dq_i[10]),
.T (ddr3_dq_en),
);
IOBUF ddr3_dq11 (
.I (ddr3_dq_o[11]),
.IO(ddr3_dq[11]),
.O (ddr3_dq_i[11]),
.T (ddr3_dq_en),
);
IOBUF ddr3_dq12 (
.I (ddr3_dq_o[12]),
.IO(ddr3_dq[12]),
.O (ddr3_dq_i[12]),
.T (ddr3_dq_en),
);
IOBUF ddr3_dq13 (
.I (ddr3_dq_o[13]),
.IO(ddr3_dq[13]),
.O (ddr3_dq_i[13]),
.T (ddr3_dq_en),
);
IOBUF ddr3_dq14 (
.I (ddr3_dq_o[14]),
.IO(ddr3_dq[14]),
.O (ddr3_dq_i[14]),
.T (ddr3_dq_en),
);
IOBUF ddr3_dq15 (
.I (ddr3_dq_o[15]),
.IO(ddr3_dq[15]),
.O (ddr3_dq_i[15]),
.T (ddr3_dq_en),
);
IOBUFDS ddr3_dqs0 (
.I (ddr3_dqs_o[0]),
.IO (ddr3_dqs0_p),
.IOB(ddr3_dqs0_n),
.O (ddr3_dqs_i[0]),
.T (ddr3_dqs_en),
);
IOBUFDS ddr3_dqs1 (
.I (ddr3_dqs_o[1]),
.IO (ddr3_dqs1_p),
.IOB(ddr3_dqs1_n),
.O (ddr3_dqs_i[1]),
.T (ddr3_dqs_en),
);
ddr3l ram ( ddr3l ram (
.reset (ddr3_reset), .reset (ddr3_reset),
.odt (ddr3_odt), .odt (ddr3_odt),
.a0 (ddr3_a0), .a (ddr3_a),
.a1 (ddr3_a1), .ba (ddr3_ba),
.a2 (ddr3_a2), .cs (ddr3_cs),
.a3 (ddr3_a3), .ras (ddr3_ras),
.a4 (ddr3_a4), .cas (ddr3_cas),
.a5 (ddr3_a5), .we (ddr3_we),
.a6 (ddr3_a6), .cke (ddr3_cke0),
.a7 (ddr3_a7), .clk (ddr3_clk),
.a8 (ddr3_a8), .dm (ddr3_dm),
.a9 (ddr3_a9), .dq_i (ddr3_dq_i),
.a10 (ddr3_a10), .dq_o (ddr3_dq_o),
.a11 (ddr3_a11), .dq_en (ddr3_dq_en),
.a12 (ddr3_a12), .dqs_i (ddr3_dqs_i),
.a13 (ddr3_a13), .dqs_o (ddr3_dqs_o),
.ba0 (ddr3_ba0), .dqs_en(ddr3_dqs_en),
.ba1 (ddr3_ba1),
.ba2 (ddr3_ba2),
.cs (ddr3_cs),
.ras (ddr3_ras),
.cas (ddr3_cas),
.we (ddr3_we),
.cke0 (ddr3_cke0),
.clk0_p (ddr3_clk0_p),
.clk0_n (ddr3_clk0_n),
.dm0 (ddr3_dm0),
.dm1 (ddr3_dm1),
.dq0 (ddr3_dq0),
.dq1 (ddr3_dq1),
.dq2 (ddr3_dq2),
.dq3 (ddr3_dq3),
.dq4 (ddr3_dq4),
.dq5 (ddr3_dq5),
.dq6 (ddr3_dq6),
.dq7 (ddr3_dq7),
.dq8 (ddr3_dq8),
.dq9 (ddr3_dq9),
.dq10 (ddr3_dq10),
.dq11 (ddr3_dq11),
.dq12 (ddr3_dq12),
.dq13 (ddr3_dq13),
.dq14 (ddr3_dq14),
.dq15 (ddr3_dq15),
.dqs0_p (ddr3_dqs0_p),
.dqs0_n (ddr3_dqs0_n),
.dqs1_p (ddr3_dqs1_p),
.dqs1_n (ddr3_dqs1_n)
); );
endmodule endmodule