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feat(dvi): increase addr width to 24

This commit is contained in:
Luca 2024-10-25 20:26:58 +02:00
parent 3d91b7e16f
commit 195990d2b1
2 changed files with 6 additions and 5 deletions
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4
dvi.v
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@ -1,5 +1,5 @@
module dvi #( module dvi #(
parameter [15:0] BASE_ADDR = 16'h0000, parameter [23:0] BASE_ADDR = 24'h000000,
parameter H_ACTIVE_START = 136, parameter H_ACTIVE_START = 136,
parameter H_BLANK_START = 792, parameter H_BLANK_START = 792,
@ -19,7 +19,7 @@ module dvi #(
) ( ) (
input bus_clk, input bus_clk,
input [15:0] bus_data, input [15:0] bus_data,
output reg [15:0] bus_addr, output reg [23:0] bus_addr,
input reset, input reset,

7
pixelflut.v
View File

@ -33,12 +33,13 @@ module pixelflut (
dvi_bus_clk <= ~dvi_bus_clk; dvi_bus_clk <= ~dvi_bus_clk;
end end
wire [15:0] dvi_bus; wire [15:0] dvi_bus_data;
wire [23:0] dvi_bus_addr;
dvi display ( dvi display (
.bus_clk (dvi_bus_clk), .bus_clk (dvi_bus_clk),
.bus_data(dvi_bus), .bus_data(dvi_bus_data),
.bus_addr(dvi_bus), .bus_addr(dvi_bus_addr),
.reset (1'b0), .reset (1'b0),
.d (dvi_d), .d (dvi_d),
.ck (dvi_ck), .ck (dvi_ck),