23 lines
377 B
Verilog
23 lines
377 B
Verilog
module ddr3l (
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output reset,
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output odt,
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output [13:0] a,
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output [2:0] ba,
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output cs,
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output ras,
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output cas,
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output we,
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output cke,
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output clk,
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output [1:0] dm,
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input [15:0] dq_i,
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output [15:0] dq_o,
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output dq_en,
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input [1:0] dqs_i,
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output [1:0] dqs_o,
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output dqs_en,
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);
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endmodule
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