52 lines
667 B
Verilog
52 lines
667 B
Verilog
module ddr3l (
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output reset,
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output odt,
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output a0,
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output a1,
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output a2,
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output a3,
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output a4,
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output a5,
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output a6,
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output a7,
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output a8,
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output a9,
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output a10,
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output a11,
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output a12,
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output a13,
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output ba0,
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output ba1,
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output ba2,
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output cs,
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output ras,
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output cas,
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output we,
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output cke0,
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output clk0_p,
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output clk0_n,
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output dm0,
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output dm1,
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inout dq0,
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inout dq1,
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inout dq2,
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inout dq3,
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inout dq4,
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inout dq5,
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inout dq6,
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inout dq7,
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inout dq8,
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inout dq9,
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inout dq10,
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inout dq11,
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inout dq12,
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inout dq13,
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inout dq14,
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inout dq15,
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inout dqs0_p,
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inout dqs0_n,
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inout dqs1_p,
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inout dqs1_n,
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);
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endmodule
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