24 lines
443 B
Verilog
24 lines
443 B
Verilog
module pixelflut (
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input sys_clk,
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output led0_r,
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output led0_g,
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output led0_b,
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);
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reg [31:0] ctr;
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reg [2:0] led0_state = 3'b0;
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assign led0_r = led0_state[0];
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assign led0_g = led0_state[1];
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assign led0_b = led0_state[2];
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always @(posedge sys_clk) begin
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if (ctr == 32'd50_000_000) begin
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ctr <= 32'b0;
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led0_state <= led0_state + 1'b1;
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end else begin
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ctr <= ctr + 1'b1;
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end
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end
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endmodule
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