200 lines
3.3 KiB
Verilog
200 lines
3.3 KiB
Verilog
module pixelflut (
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input sys_clk,
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output led0_r,
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output led0_g,
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output led0_b,
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output ddr3_reset,
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output ddr3_odt,
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output [13:0] ddr3_a,
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output [2:0] ddr3_ba,
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output ddr3_cs,
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output ddr3_ras,
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output ddr3_cas,
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output ddr3_we,
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output ddr3_cke0,
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output ddr3_clk0_p,
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output ddr3_clk0_n,
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output [1:0] ddr3_dm,
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inout [15:0] ddr3_dq,
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inout ddr3_dqs0_p,
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inout ddr3_dqs0_n,
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inout ddr3_dqs1_p,
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inout ddr3_dqs1_n,
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);
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reg [31:0] ctr;
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reg [2:0] led0_state = 3'b0;
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assign led0_r = led0_state[0];
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assign led0_g = led0_state[1];
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assign led0_b = led0_state[2];
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always @(posedge sys_clk) begin
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if (ctr == 32'd50_000_000) begin
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ctr <= 32'b0;
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led0_state <= led0_state + 1'b1;
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end else begin
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ctr <= ctr + 1'b1;
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end
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end
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wire ddr3_clk, ddr3_dq_en, ddr3_dqs_en;
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wire [15:0] ddr3_dq_i, ddr3_dq_o;
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wire [1:0] ddr3_dqs_i, ddr3_dqs_o;
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OBUFDS ddr3_clk0 (
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.I (ddr3_clk),
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.O (ddr3_clk0_p),
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.OB(ddr3_clk0_n),
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);
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IOBUF ddr3_dq0 (
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.I (ddr3_dq_o[0]),
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.IO(ddr3_dq[0]),
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.O (ddr3_dq_i[0]),
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.T (ddr3_dq_en),
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);
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IOBUF ddr3_dq1 (
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.I (ddr3_dq_o[1]),
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.IO(ddr3_dq[1]),
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.O (ddr3_dq_i[1]),
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.T (ddr3_dq_en),
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);
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IOBUF ddr3_dq2 (
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.I (ddr3_dq_o[2]),
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.IO(ddr3_dq[2]),
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.O (ddr3_dq_i[2]),
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.T (ddr3_dq_en),
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);
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IOBUF ddr3_dq3 (
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.I (ddr3_dq_o[3]),
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.IO(ddr3_dq[3]),
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.O (ddr3_dq_i[3]),
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.T (ddr3_dq_en),
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);
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IOBUF ddr3_dq4 (
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.I (ddr3_dq_o[4]),
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.IO(ddr3_dq[4]),
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.O (ddr3_dq_i[4]),
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.T (ddr3_dq_en),
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);
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IOBUF ddr3_dq5 (
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.I (ddr3_dq_o[5]),
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.IO(ddr3_dq[5]),
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.O (ddr3_dq_i[5]),
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.T (ddr3_dq_en),
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);
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IOBUF ddr3_dq6 (
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.I (ddr3_dq_o[6]),
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.IO(ddr3_dq[6]),
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.O (ddr3_dq_i[6]),
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.T (ddr3_dq_en),
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);
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IOBUF ddr3_dq7 (
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.I (ddr3_dq_o[7]),
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.IO(ddr3_dq[7]),
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.O (ddr3_dq_i[7]),
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.T (ddr3_dq_en),
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);
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IOBUF ddr3_dq8 (
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.I (ddr3_dq_o[8]),
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.IO(ddr3_dq[8]),
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.O (ddr3_dq_i[8]),
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.T (ddr3_dq_en),
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);
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IOBUF ddr3_dq9 (
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.I (ddr3_dq_o[9]),
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.IO(ddr3_dq[9]),
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.O (ddr3_dq_i[9]),
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.T (ddr3_dq_en),
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);
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IOBUF ddr3_dq10 (
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.I (ddr3_dq_o[10]),
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.IO(ddr3_dq[10]),
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.O (ddr3_dq_i[10]),
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.T (ddr3_dq_en),
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);
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IOBUF ddr3_dq11 (
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.I (ddr3_dq_o[11]),
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.IO(ddr3_dq[11]),
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.O (ddr3_dq_i[11]),
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.T (ddr3_dq_en),
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);
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IOBUF ddr3_dq12 (
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.I (ddr3_dq_o[12]),
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.IO(ddr3_dq[12]),
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.O (ddr3_dq_i[12]),
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.T (ddr3_dq_en),
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);
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IOBUF ddr3_dq13 (
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.I (ddr3_dq_o[13]),
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.IO(ddr3_dq[13]),
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.O (ddr3_dq_i[13]),
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.T (ddr3_dq_en),
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);
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IOBUF ddr3_dq14 (
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.I (ddr3_dq_o[14]),
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.IO(ddr3_dq[14]),
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.O (ddr3_dq_i[14]),
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.T (ddr3_dq_en),
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);
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IOBUF ddr3_dq15 (
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.I (ddr3_dq_o[15]),
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.IO(ddr3_dq[15]),
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.O (ddr3_dq_i[15]),
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.T (ddr3_dq_en),
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);
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IOBUFDS ddr3_dqs0 (
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.I (ddr3_dqs_o[0]),
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.IO (ddr3_dqs0_p),
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.IOB(ddr3_dqs0_n),
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.O (ddr3_dqs_i[0]),
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.T (ddr3_dqs_en),
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);
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IOBUFDS ddr3_dqs1 (
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.I (ddr3_dqs_o[1]),
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.IO (ddr3_dqs1_p),
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.IOB(ddr3_dqs1_n),
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.O (ddr3_dqs_i[1]),
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.T (ddr3_dqs_en),
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);
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ddr3l ram (
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.reset (ddr3_reset),
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.odt (ddr3_odt),
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.a (ddr3_a),
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.ba (ddr3_ba),
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.cs (ddr3_cs),
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.ras (ddr3_ras),
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.cas (ddr3_cas),
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.we (ddr3_we),
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.cke (ddr3_cke0),
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.clk (ddr3_clk),
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.dm (ddr3_dm),
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.dq_i (ddr3_dq_i),
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.dq_o (ddr3_dq_o),
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.dq_en (ddr3_dq_en),
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.dqs_i (ddr3_dqs_i),
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.dqs_o (ddr3_dqs_o),
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.dqs_en(ddr3_dqs_en),
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);
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endmodule
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