126 lines
2.3 KiB
Verilog
126 lines
2.3 KiB
Verilog
module pixelflut (
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input sys_clk,
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output led0_r,
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output led0_g,
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output led0_b,
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output [11:0] dvi_d,
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output dvi_ck,
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output dvi_de,
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output dvi_hs,
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output dvi_vs,
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output eth_mdc,
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inout eth_mdio,
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output eth_ref_clk,
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output eth_rstn,
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input eth_rx_clk,
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input eth_rx_dv,
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input [3:0] eth_rxd,
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input eth_rxerr,
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input eth_tx_clk,
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output eth_tx_en,
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output [3:0] eth_txd,
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);
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reg [31:0] ctr;
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reg [2:0] led0_state;
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assign led0_r = led0_state[0];
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assign led0_g = led0_state[1];
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assign led0_b = led0_state[2];
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initial begin
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led0_state <= 3'b0;
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end
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always @(posedge sys_clk) begin
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if (ctr == 32'd50_000_000) begin
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ctr <= 32'b0;
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led0_state <= led0_state + 1'b1;
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end else begin
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ctr <= ctr + 1'b1;
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end
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end
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reg dvi_bus_clk;
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always @(posedge sys_clk) begin
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dvi_bus_clk <= ~dvi_bus_clk;
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end
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wire [15:0] dvi_bus_data;
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wire [23:0] dvi_bus_addr;
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dvi display (
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.bus_clk (dvi_bus_clk),
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.bus_data(dvi_bus_data),
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.bus_addr(dvi_bus_addr),
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.reset (1'b0),
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.d (dvi_d),
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.ck (dvi_ck),
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.de (dvi_de),
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.hs (dvi_hs),
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.vs (dvi_vs),
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);
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reg [1:0] eth_clk_div;
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assign eth_ref_clk = eth_clk_div[1];
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initial begin
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eth_clk_div <= 2'b0;
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end
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always @(posedge sys_clk) begin
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eth_clk_div <= eth_clk_div + 1;
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end
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assign eth_rstn = 1;
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assign eth_tx_en = 0;
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assign eth_txd = 4'b0;
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wire eth_mdio_i, eth_mdio_o, eth_mdio_en;
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IOBUF eth_mdio_buf (
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.I (eth_mdio_o),
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.IO(eth_mdio),
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.O (eth_mdio_i),
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.T (eth_mdio_en),
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);
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ethernet_smi smi (
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.clk (sys_clk),
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.mdio_i (eth_mdio_i),
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.mdio_o (eth_mdio_o),
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.mdio_en(eth_mdio_en),
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.mdc (eth_mdc),
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);
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wire eth_bus_clk;
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wire [15:0] eth_bus_data;
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wire [23:0] eth_bus_addr;
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wire [1:0] eth_bus_sel;
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pingxelflut eth (
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.rx_clk (eth_rx_clk),
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.rxd (eth_rxd),
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.rx_dv (eth_rx_dv),
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.rx_er (eth_rxerr),
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.bus_clk (eth_bus_clk),
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.bus_data(eth_bus_data),
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.bus_addr(eth_bus_addr),
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.bus_sel (eth_bus_sel),
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);
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xc7_bram ram (
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.out_clk (dvi_bus_clk),
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.out_data(dvi_bus_data),
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.out_addr(dvi_bus_addr),
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.in_clk (eth_bus_clk),
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.in_data (eth_bus_data),
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.in_addr (eth_bus_addr),
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.in_wren (eth_bus_sel),
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);
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endmodule
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