fix(dvi): simulation

Makefile

@@ -15,7 +15,6 @@ prog: pixelflut.bit
 	openFPGALoader -b arty_a7_35t $<
 
 sim: dvi_tb.vcd
-	gtkwave $<
 
 pixelflut.bit: pixelflut.frames
 	xc7frames2bit --part_file "$(XRAY_DATABASE_DIR)/artix7/$(PART)/part.yaml" --part_name $(PART) --frm_file $< --output_file $@

dvi.v

@@ -100,10 +100,12 @@ module dvi #(
 
 			if (y == V_DATA_START && (~ck && x == H_DATA_START-3 || x >= H_DATA_START-2) && x < H_DATA_START) fetch_en <= 1;
 
-			if (y >= V_DATA_START && y < V_DATA_END && x >= H_DATA_START && x < H_DATA_END) begin
-				d <= data[active_data][11:0];
+			if (y >= V_DATA_START && y < V_DATA_END) begin
+				if ((~ck && x == H_DATA_START-1 || x >= H_DATA_START) && (x <= H_DATA_END-2 || ck && x == H_DATA_END-1)) begin
+					d <= data[active_data][11:0];
 
-				fetch_en <= 1;
+					fetch_en <= 1;
+				end
 			end
 
 			if (x == H_BLANK_START-1) begin
@@ -117,8 +119,8 @@ module dvi #(
 	end
 
 	always @(negedge bus_clk) begin
-		if (output_state == OUTPUT_IDLE) ck <= 0;
-		else                             ck <= ~ck;
+		if (output_state == OUTPUT_IDLE || ck == 1) ck <= 0;
+		else                                        ck <= 1;
 
 		if (y == 11'b0) begin
 			bus_addr <= BASE_ADDR;

dvi_tb.v

@@ -5,13 +5,13 @@ module testbench();
 
 	always #10 clk = ~clk;
 
-	wire [15:0] addr;
+	wire [23:0] addr;
 	wire [11:0] d;
 	wire        ck, de, hs, vs;
 
 	dvi display (
 		.bus_clk (clk),
-		.bus_data(addr),
+		.bus_data(addr[15:0]),
 		.bus_addr(addr),
 
 		.reset   (1'b0),