luca
/
pixelflut
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Compare commits

base: luca:67b3c305c334bf4837dbb8f9fba6f9fbb7683ce1
Branches Tags
luca:main
..
compare: luca:6b988087bd470501f0ad5f9dfc4dbcd6ccfd08e7
Branches Tags
luca:main

No commits in common. "67b3c305c334bf4837dbb8f9fba6f9fbb7683ce1" and "6b988087bd470501f0ad5f9dfc4dbcd6ccfd08e7" have entirely different histories.
67b3c305c3 ... 6b988087bd

3 changed files with 8 additions and 9 deletions
Show Stats Expand all files Collapse all files

1
Makefile
View File

@ -15,6 +15,7 @@ prog: pixelflut.bit
openFPGALoader -b arty_a7_35t $<
sim: dvi_tb.vcd
gtkwave $<
pixelflut.bit: pixelflut.frames
xc7frames2bit --part_file "$(XRAY_DATABASE_DIR)/artix7/$(PART)/part.yaml" --part_name $(PART) --frm_file $< --output_file $@

12
dvi.v
View File

@ -100,12 +100,10 @@ module dvi #(
if (y == V_DATA_START && (~ck && x == H_DATA_START-3 || x >= H_DATA_START-2) && x < H_DATA_START) fetch_en <= 1;
if (y >= V_DATA_START && y < V_DATA_END) begin
if ((~ck && x == H_DATA_START-1 || x >= H_DATA_START) && (x <= H_DATA_END-2 || ck && x == H_DATA_END-1)) begin
d <= data[active_data][11:0];
if (y >= V_DATA_START && y < V_DATA_END && x >= H_DATA_START && x < H_DATA_END) begin
d <= data[active_data][11:0];
fetch_en <= 1;
end
fetch_en <= 1;
end
if (x == H_BLANK_START-1) begin
@ -119,8 +117,8 @@ module dvi #(
end
always @(negedge bus_clk) begin
if (output_state == OUTPUT_IDLE || ck == 1) ck <= 0;
else ck <= 1;
if (output_state == OUTPUT_IDLE) ck <= 0;
else ck <= ~ck;
if (y == 11'b0) begin
bus_addr <= BASE_ADDR;

4
dvi_tb.v
View File

@ -5,13 +5,13 @@ module testbench();
always #10 clk = ~clk;
wire [23:0] addr;
wire [15:0] addr;
wire [11:0] d;
wire ck, de, hs, vs;
dvi display (
.bus_clk (clk),
.bus_data(addr[15:0]),
.bus_data(addr),
.bus_addr(addr),
.reset (1'b0),