dvi.v

@@ -80,7 +80,11 @@ module dvi #(
 			x <= 12'b0;
 			y <= 11'b0;
 
-			if (~reset) output_state <= OUTPUT_BLANK;
+			if (~reset) begin
+				ck <= 0;
+
+				output_state <= OUTPUT_BLANK;
+			end
 		end
 		OUTPUT_BLANK: begin
 			if (y >= V_ACTIVE_START && y < V_BLANK_START && x == H_ACTIVE_START-1) output_state <= OUTPUT_DATA;
@@ -90,6 +94,9 @@ module dvi #(
 				y <= y + 1;
 
 				if (y == V_TOTAL-1) begin
+					bus_addr <= BASE_ADDR;
+
+					fetch_state <= FETCH_LOW;
 					y <= 11'b0;
 				end
 			end
@@ -117,14 +124,7 @@ module dvi #(
 	end
 
 	always @(negedge bus_clk) begin
-		if (output_state == OUTPUT_IDLE) ck <= 0;
-		else                             ck <= ~ck;
-
-		if (y == 11'b0) begin
-			bus_addr <= BASE_ADDR;
-
-			fetch_state <= FETCH_LOW;
-		end
+		if (output_state != OUTPUT_IDLE) ck <= ~ck;
 
 		if (fetch_en) begin
 			data[active_data] <= {12'b0, data[active_data][47:12]};

pixelflut.v

@@ -27,16 +27,10 @@ module pixelflut (
 		end
 	end
 
-	reg dvi_bus_clk;
-
-	always @(posedge sys_clk) begin
-		dvi_bus_clk <= ~dvi_bus_clk;
-	end
-
 	wire [15:0] dvi_bus;
 
 	dvi display (
-		.bus_clk (dvi_bus_clk),
+		.bus_clk (sys_clk),
 		.bus_data(dvi_bus),
 		.bus_addr(dvi_bus),
 		.reset   (1'b0),