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test(pingxelflut): add testbench

This commit is contained in:
Luca 2024-12-29 18:32:08 +01:00
parent 118355ca5b
commit d7b46ab41c
5 changed files with 244 additions and 3 deletions
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8
Makefile
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@ -14,7 +14,7 @@ clean:
prog: pixelflut.bit prog: pixelflut.bit
openFPGALoader -b arty_a7_35t $< openFPGALoader -b arty_a7_35t $<
sim: dvi_tb.vcd sim: dvi_tb.vcd pingxelflut_tb.vcd
pixelflut.bit: pixelflut.frames pixelflut.bit: pixelflut.frames
xc7frames2bit --part_file "$(XRAY_DATABASE_DIR)/artix7/$(PART)/part.yaml" --part_name $(PART) --frm_file $< --output_file $@ xc7frames2bit --part_file "$(XRAY_DATABASE_DIR)/artix7/$(PART)/part.yaml" --part_name $(PART) --frm_file $< --output_file $@
@ -33,3 +33,9 @@ dvi_tb.vcd: dvi_tb.vvp
dvi_tb.vvp: dvi_tb.v dvi.v dvi_tb.vvp: dvi_tb.v dvi.v
iverilog -o $@ $^ iverilog -o $@ $^
pingxelflut_tb.vcd: pingxelflut_tb.vvp
vvp $<
pingxelflut_tb.vvp: pingxelflut_tb.v pingxelflut.v
iverilog -o $@ $^

4
pingxelflut.v
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@ -1,7 +1,7 @@
module pingxelflut #( module pingxelflut #(
parameter MAC_ADDRESS = 48'h02_00_00_00_00_00, parameter MAC_ADDRESS = 48'h02_00_00_00_00_00,
parameter SCREEN_WIDTH = 346, parameter SCREEN_WIDTH = 346
) ( ) (
input rx_clk, input rx_clk,
input [3:0] rxd, input [3:0] rxd,
@ -11,7 +11,7 @@ module pingxelflut #(
output reg bus_clk, output reg bus_clk,
output reg [15:0] bus_data, output reg [15:0] bus_data,
output reg [23:0] bus_addr, output reg [23:0] bus_addr,
output reg [1:0] bus_sel, output reg [1:0] bus_sel
); );
localparam PREAMBLE = 7'b0000000; localparam PREAMBLE = 7'b0000000;
localparam DEST_0 = 7'b0000001; localparam DEST_0 = 7'b0000001;

64
pingxelflut_state.txt Normal file
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@ -0,0 +1,64 @@
0000000 PREAMBLE
0000001 DEST_0
0000010 DEST_1
0000011 DEST_2
0000100 DEST_3
0000101 DEST_4
0000110 DEST_5
0000111 DEST_6
0001000 DEST_7
0001001 DEST_8
0001010 DEST_9
0001011 DEST_A
0001100 DEST_B
0001101 SRC_0
0001110 SRC_1
0001111 SRC_2
0010000 SRC_3
0010001 SRC_4
0010010 SRC_5
0010011 SRC_6
0010100 SRC_7
0010101 SRC_8
0010110 SRC_9
0010111 SRC_A
0011000 SRC_B
0011001 ETHER_TYPE_0
0011010 ETHER_TYPE_1
0011011 ETHER_TYPE_2
0011100 ETHER_TYPE_3
0100000 TRAFFIC_CLASS_0
0100001 VERSION
0100010 FLOW_LABEL_0
0100011 TRAFFIC_CLASS_1
0100100 FLOW_LABEL_1
0100101 FLOW_LABEL_2
0100110 FLOW_LABEL_3
0100111 FLOW_LABEL_4
0101000 PAYLOAD_LENGTH_0
0101001 PAYLOAD_LENGTH_1
0101010 PAYLOAD_LENGTH_2
0101011 PAYLOAD_LENGTH_3
0101100 NEXT_HEADER_0
0101101 NEXT_HEADER_1
0101110 HOP_LIMIT_0
0101111 HOP_LIMIT_1
0110000 SRC_ADDR_0
1010000 DEST_PREFIX_0
1100000 X_0
1100001 X_1
1100010 X_2
1100011 X_3
1100100 Y_0
1100101 Y_1
1100110 Y_2
1100111 Y_3
1101000 RED_LOW
1101001 RED_HIGH
1101010 GREEN_LOW
1101011 GREEN_HIGH
1101100 BLUE_LOW
1101101 BLUE_HIGH
1101110 PADDING_LOW
1101111 PADDING_HIGH
1111111 IGNORE

129
pingxelflut_tb.hex Normal file
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42
pingxelflut_tb.v Normal file
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@ -0,0 +1,42 @@
`timescale 1 ns / 1 ns
module testbench();
reg clk = 0;
always #20 clk = ~clk;
reg [3:0] rxd;
wire bus_clk;
wire [15:0] bus_data;
wire [23:0] bus_addr;
wire [1:0] bus_sel;
pingxelflut eth (
.rx_clk (clk),
.rxd (rxd),
.rx_dv (1'b1),
.rx_er (1'b0),
.bus_clk (bus_clk),
.bus_data(bus_data),
.bus_addr(bus_addr),
.bus_sel (bus_sel)
);
reg [3:0] test_data [0:128];
initial begin
$dumpfile("pingxelflut_tb.vcd");
$dumpvars(0, testbench);
$readmemh("pingxelflut_tb.hex", test_data);
rxd <= test_data[0];
#10;
for (integer i = 1; i < 129; i = i + 1) #40 rxd <= test_data[i];
$finish;
end
endmodule