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chore(dvi_tb): increase addr width to 24

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Luca 2024-12-29 01:58:35 +01:00
parent 72982a095b
commit a615feb504
1 changed files with 2 additions and 2 deletions
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dvi_tb.v
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@ -5,13 +5,13 @@ module testbench();
always #10 clk = ~clk; always #10 clk = ~clk;
wire [15:0] addr; wire [23:0] addr;
wire [11:0] d; wire [11:0] d;
wire ck, de, hs, vs; wire ck, de, hs, vs;
dvi display ( dvi display (
.bus_clk (clk), .bus_clk (clk),
.bus_data(addr), .bus_data(addr[15:0]),
.bus_addr(addr), .bus_addr(addr),
.reset (1'b0), .reset (1'b0),