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fix(dvi): simulation

This commit is contained in:
Luca 2024-12-29 02:00:37 +01:00
parent b414b53571
commit 67b3c305c3
1 changed files with 2 additions and 2 deletions
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4
dvi.v
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@ -119,8 +119,8 @@ module dvi #(
end end
always @(negedge bus_clk) begin always @(negedge bus_clk) begin
if (output_state == OUTPUT_IDLE) ck <= 0; if (output_state == OUTPUT_IDLE || ck == 1) ck <= 0;
else ck <= ~ck; else ck <= 1;
if (y == 11'b0) begin if (y == 11'b0) begin
bus_addr <= BASE_ADDR; bus_addr <= BASE_ADDR;