fix(xc7_bram): set all trailing address bits to 1
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@ -15,8 +15,8 @@ module xc7_bram #(
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assign out_data = porta_out[out_addr[16:11]][15:0];
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assign porta_addr = {1'b1, out_addr[10:0], 4'b1};
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assign portb_addr = {1'b1, in_addr[10:0], 4'b1};
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assign porta_addr = {1'b1, out_addr[10:0], 4'b1111};
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assign portb_addr = {1'b1, in_addr[10:0], 4'b1111};
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genvar i;
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