fix: divide sys_clk by 2 for dvi_bus_clk

2024-10-19 20:24:40 +02:00 · 2024-10-19 20:24:40 +02:00 · 3d91b7e16f
parent e6676cc995
commit 3d91b7e16f
1 changed files with 7 additions and 1 deletions
--- a/pixelflut.v
+++ b/pixelflut.v
@ -27,10 +27,16 @@ module pixelflut (
 		end
 	end

+	reg dvi_bus_clk;
+
+	always @(posedge sys_clk) begin
+		dvi_bus_clk <= ~dvi_bus_clk;
+	end
+
 	wire [15:0] dvi_bus;

 	dvi display (
-		.bus_clk (sys_clk),
+		.bus_clk (dvi_bus_clk),
 		.bus_data(dvi_bus),
 		.bus_addr(dvi_bus),
 		.reset   (1'b0),