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fix: divide sys_clk by 2 for dvi_bus_clk

This commit is contained in:
Luca 2024-10-19 20:24:40 +02:00
parent e6676cc995
commit 3d91b7e16f
1 changed files with 7 additions and 1 deletions
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8
pixelflut.v
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@ -27,10 +27,16 @@ module pixelflut (
end end
end end
reg dvi_bus_clk;
always @(posedge sys_clk) begin
dvi_bus_clk <= ~dvi_bus_clk;
end
wire [15:0] dvi_bus; wire [15:0] dvi_bus;
dvi display ( dvi display (
.bus_clk (sys_clk), .bus_clk (dvi_bus_clk),
.bus_data(dvi_bus), .bus_data(dvi_bus),
.bus_addr(dvi_bus), .bus_addr(dvi_bus),
.reset (1'b0), .reset (1'b0),