chore: add testbench for dvi module

.gitignore

@@ -1,6 +1,7 @@
 *.bit
 *.fasm
 *.frames
+*.gtkw
 *.json
 *.vcd
 *.vvp

Makefile

@@ -3,16 +3,20 @@ XRAY_DATABASE_DIR = /usr/share/xray/database
 
 PART = xc7a35tcsg324-1
 
-.PHONY: all clean prog
+.PHONY: all clean prog sim
 
 all: pixelflut.bit
 
 clean:
 	rm -f pixelflut.bit pixelflut.fasm pixelflut.frames pixelflut.json
+	rm -f dvi_tb.vcd dvi_tb.vvp
 
 prog: pixelflut.bit
 	openFPGALoader -b arty_a7_35t $<
 
+sim: dvi_tb.vcd
+	gtkwave $<
+
 pixelflut.bit: pixelflut.frames
 	xc7frames2bit --part_file "$(XRAY_DATABASE_DIR)/artix7/$(PART)/part.yaml" --part_name $(PART) --frm_file $< --output_file $@
 
@@ -24,3 +28,9 @@ pixelflut.fasm: arty_a7_35t.xdc pixelflut.json
 
 pixelflut.json: pixelflut.v dvi.v
 	yosys -q -p 'synth_xilinx -top pixelflut; write_json $@' $^
+
+dvi_tb.vcd: dvi_tb.vvp
+	vvp $<
+
+dvi_tb.vvp: dvi_tb.v dvi.v
+	iverilog -o $@ $^

dvi_tb.v

@@ -0,0 +1,32 @@
+`timescale 1 ns / 1 ns
+
+module testbench();
+	reg clk = 0;
+
+	always #10 clk = ~clk;
+
+	wire [15:0] addr;
+	wire [11:0] d;
+	wire        ck, de, hs, vs;
+
+	dvi display (
+		.bus_clk (clk),
+		.bus_data(addr),
+		.bus_addr(addr),
+
+		.reset   (1'b0),
+
+		.d       (d),
+		.ck      (ck),
+		.de      (de),
+		.hs      (hs),
+		.vs      (vs)
+	);
+
+	initial begin
+		$dumpfile("dvi_tb.vcd");
+		$dumpvars(0, testbench);
+		#16800040;
+		$finish;
+	end
+endmodule

fetch_state.txt

@@ -0,0 +1,4 @@
+00 Low
+01 Mid
+10 High
+11 Swap

output_state.txt

@@ -0,0 +1,4 @@
+00 Idle
+01 Blank
+10 Data
+11 Invalid