124 lines
2.3 KiB
Coq
124 lines
2.3 KiB
Coq
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module pixelflut (
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input sys_clk,
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output led0_r,
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output led0_g,
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output led0_b,
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output ddr3_reset,
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output ddr3_odt,
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output ddr3_a0,
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output ddr3_a1,
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output ddr3_a2,
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output ddr3_a3,
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output ddr3_a4,
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output ddr3_a5,
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output ddr3_a6,
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output ddr3_a7,
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output ddr3_a8,
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output ddr3_a9,
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output ddr3_a10,
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output ddr3_a11,
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output ddr3_a12,
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output ddr3_a13,
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output ddr3_ba0,
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output ddr3_ba1,
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output ddr3_ba2,
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output ddr3_cs,
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output ddr3_ras,
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output ddr3_cas,
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output ddr3_we,
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output ddr3_cke0,
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output ddr3_clk0_p,
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output ddr3_clk0_n,
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output ddr3_dm0,
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output ddr3_dm1,
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inout ddr3_dq0,
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inout ddr3_dq1,
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inout ddr3_dq2,
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inout ddr3_dq3,
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inout ddr3_dq4,
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inout ddr3_dq5,
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inout ddr3_dq6,
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inout ddr3_dq7,
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inout ddr3_dq8,
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inout ddr3_dq9,
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inout ddr3_dq10,
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inout ddr3_dq11,
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inout ddr3_dq12,
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inout ddr3_dq13,
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inout ddr3_dq14,
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inout ddr3_dq15,
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inout ddr3_dqs0_p,
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inout ddr3_dqs0_n,
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inout ddr3_dqs1_p,
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inout ddr3_dqs1_n,
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);
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reg [31:0] ctr;
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reg [2:0] led0_state = 3'b0;
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assign led0_r = led0_state[0];
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assign led0_g = led0_state[1];
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assign led0_b = led0_state[2];
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always @(posedge sys_clk) begin
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if (ctr == 32'd50_000_000) begin
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ctr <= 32'b0;
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led0_state <= led0_state + 1'b1;
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end else begin
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ctr <= ctr + 1'b1;
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end
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end
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ddr3l ram (
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.reset (ddr3_reset),
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.odt (ddr3_odt),
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.a0 (ddr3_a0),
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.a1 (ddr3_a1),
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.a2 (ddr3_a2),
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.a3 (ddr3_a3),
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.a4 (ddr3_a4),
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.a5 (ddr3_a5),
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.a6 (ddr3_a6),
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.a7 (ddr3_a7),
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.a8 (ddr3_a8),
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.a9 (ddr3_a9),
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.a10 (ddr3_a10),
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.a11 (ddr3_a11),
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.a12 (ddr3_a12),
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.a13 (ddr3_a13),
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.ba0 (ddr3_ba0),
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.ba1 (ddr3_ba1),
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.ba2 (ddr3_ba2),
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.cs (ddr3_cs),
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.ras (ddr3_ras),
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.cas (ddr3_cas),
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.we (ddr3_we),
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.cke0 (ddr3_cke0),
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.clk0_p (ddr3_clk0_p),
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.clk0_n (ddr3_clk0_n),
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.dm0 (ddr3_dm0),
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.dm1 (ddr3_dm1),
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.dq0 (ddr3_dq0),
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.dq1 (ddr3_dq1),
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.dq2 (ddr3_dq2),
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.dq3 (ddr3_dq3),
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.dq4 (ddr3_dq4),
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.dq5 (ddr3_dq5),
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.dq6 (ddr3_dq6),
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.dq7 (ddr3_dq7),
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.dq8 (ddr3_dq8),
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.dq9 (ddr3_dq9),
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.dq10 (ddr3_dq10),
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.dq11 (ddr3_dq11),
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.dq12 (ddr3_dq12),
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.dq13 (ddr3_dq13),
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.dq14 (ddr3_dq14),
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.dq15 (ddr3_dq15),
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.dqs0_p (ddr3_dqs0_p),
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.dqs0_n (ddr3_dqs0_n),
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.dqs1_p (ddr3_dqs1_p),
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.dqs1_n (ddr3_dqs1_n)
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);
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endmodule
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