42 lines
926 B
Coq
42 lines
926 B
Coq
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module xc7_bram #(
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parameter NUM_BLOCKS = 50,
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) (
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input out_clk,
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output [15:0] out_data,
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input [23:0] out_addr,
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input in_clk,
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input [15:0] in_data,
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input [23:0] in_addr,
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input [1:0] in_wren,
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);
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wire [31:0] porta_out [NUM_BLOCKS-1:0];
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wire [15:0] porta_addr, portb_addr;
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assign out_data = porta_out[out_addr[16:11]][15:0];
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assign porta_addr = {1'b1, out_addr[10:0], 4'b1};
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assign portb_addr = {1'b1, in_addr[10:0], 4'b1};
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genvar i;
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generate
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for (i = 0; i < NUM_BLOCKS; i = i + 1) begin
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RAMB36E1 #(
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.READ_WIDTH_A (18),
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.WRITE_WIDTH_B(18),
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) bram_block (
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.DOADO (porta_out[i]),
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.ADDRARDADDR(porta_addr),
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.CLKARDCLK (out_clk),
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.ENARDEN (1'b1),
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.ADDRBWRADDR(portb_addr),
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.CLKBWRCLK (in_clk),
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.ENBWREN (in_addr[16:11] == i),
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.WEBWE ({6'b0, in_wren}),
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.DIBDI ({16'h0000, in_data}),
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);
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end
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endgenerate
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endmodule
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