chore: create schematic and place components

This commit is contained in:
Luca 2025-02-15 22:05:20 +01:00
parent 509717ade0
commit 48fac93b3b
3 changed files with 25114 additions and 13 deletions

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@ -48,10 +48,16 @@
"silk_text_thickness": 0.1, "silk_text_thickness": 0.1,
"silk_text_upright": false, "silk_text_upright": false,
"zones": { "zones": {
"min_clearance": 0.5 "min_clearance": 0.15
} }
}, },
"diff_pair_dimensions": [], "diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [], "drc_exclusions": [],
"meta": { "meta": {
"version": 2 "version": 2
@ -171,7 +177,9 @@
"td_width_to_size_filter_ratio": 0.9 "td_width_to_size_filter_ratio": 0.9
} }
], ],
"track_widths": [], "track_widths": [
0.0
],
"tuning_pattern_settings": { "tuning_pattern_settings": {
"diff_pair_defaults": { "diff_pair_defaults": {
"corner_radius_percentage": 80, "corner_radius_percentage": 80,
@ -198,7 +206,12 @@
"spacing": 0.6 "spacing": 0.6
} }
}, },
"via_dimensions": [], "via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
}
],
"zones_allow_external_fillets": false "zones_allow_external_fillets": false
}, },
"ipc2581": { "ipc2581": {
@ -438,7 +451,7 @@
"classes": [ "classes": [
{ {
"bus_width": 12, "bus_width": 12,
"clearance": 0.2, "clearance": 0.15,
"diff_pair_gap": 0.25, "diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25, "diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2, "diff_pair_width": 0.2,
@ -448,10 +461,78 @@
"name": "Default", "name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)", "pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)", "schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.15,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.5,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Earth",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.5,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.15,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.1326,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "MDI",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2, "track_width": 0.2,
"via_diameter": 0.6, "via_diameter": 0.6,
"via_drill": 0.3, "via_drill": 0.3,
"wire_width": 6 "wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.15,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "MII",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.1565,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.15,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Power",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
} }
], ],
"meta": { "meta": {
@ -459,7 +540,24 @@
}, },
"net_colors": null, "net_colors": null,
"netclass_assignments": null, "netclass_assignments": null,
"netclass_patterns": [] "netclass_patterns": [
{
"netclass": "MDI",
"pattern": "/MDI??"
},
{
"netclass": "Earth",
"pattern": "Earth"
},
{
"netclass": "MII",
"pattern": "/[RT]X(C|CTL|D[0123])"
},
{
"netclass": "Power",
"pattern": "\\+1V0|\\+3V3|GND"
}
]
}, },
"pcbnew": { "pcbnew": {
"last_paths": { "last_paths": {
@ -574,6 +672,11 @@
"subpart_first_id": 65, "subpart_first_id": 65,
"subpart_id_separator": 0 "subpart_id_separator": 0
}, },
"sheets": [], "sheets": [
[
"26e42519-9131-4e8e-bd7a-4a55637877a0",
"Root"
]
],
"text_variables": {} "text_variables": {}
} }

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