module pixelflut (
	input         sys_clk,

	output        led0_r,
	output        led0_g,
	output        led0_b,

	output [11:0] dvi_d,
	output        dvi_ck,
	output        dvi_de,
	output        dvi_hs,
	output        dvi_vs,
);
	reg [31:0] ctr;
	reg  [2:0] led0_state = 3'b0;

	assign led0_r = led0_state[0];
	assign led0_g = led0_state[1];
	assign led0_b = led0_state[2];

	always @(posedge sys_clk) begin
		if (ctr == 32'd50_000_000) begin
			ctr <= 32'b0;
			led0_state <= led0_state + 1'b1;
		end else begin
			ctr <= ctr + 1'b1;
		end
	end

	wire [15:0] dvi_bus;

	dvi display (
		.bus_clk (sys_clk),
		.bus_data(dvi_bus),
		.bus_addr(dvi_bus),
		.reset   (1'b0),
		.d       (dvi_d),
		.ck      (dvi_ck),
		.de      (dvi_de),
		.hs      (dvi_hs),
		.vs      (dvi_vs),
	);
endmodule