module pixelflut (
	input  sys_clk,

	output led0_r,
	output led0_g,
	output led0_b,

	output ddr3_reset,
	output ddr3_odt,
	output ddr3_a0,
	output ddr3_a1,
	output ddr3_a2,
	output ddr3_a3,
	output ddr3_a4,
	output ddr3_a5,
	output ddr3_a6,
	output ddr3_a7,
	output ddr3_a8,
	output ddr3_a9,
	output ddr3_a10,
	output ddr3_a11,
	output ddr3_a12,
	output ddr3_a13,
	output ddr3_ba0,
	output ddr3_ba1,
	output ddr3_ba2,
	output ddr3_cs,
	output ddr3_ras,
	output ddr3_cas,
	output ddr3_we,
	output ddr3_cke0,
	output ddr3_clk0_p,
	output ddr3_clk0_n,
	output ddr3_dm0,
	output ddr3_dm1,
	inout  ddr3_dq0,
	inout  ddr3_dq1,
	inout  ddr3_dq2,
	inout  ddr3_dq3,
	inout  ddr3_dq4,
	inout  ddr3_dq5,
	inout  ddr3_dq6,
	inout  ddr3_dq7,
	inout  ddr3_dq8,
	inout  ddr3_dq9,
	inout  ddr3_dq10,
	inout  ddr3_dq11,
	inout  ddr3_dq12,
	inout  ddr3_dq13,
	inout  ddr3_dq14,
	inout  ddr3_dq15,
	inout  ddr3_dqs0_p,
	inout  ddr3_dqs0_n,
	inout  ddr3_dqs1_p,
	inout  ddr3_dqs1_n,
);
	reg [31:0] ctr;
	reg  [2:0] led0_state = 3'b0;

	assign led0_r = led0_state[0];
	assign led0_g = led0_state[1];
	assign led0_b = led0_state[2];

	always @(posedge sys_clk) begin
		if (ctr == 32'd50_000_000) begin
			ctr <= 32'b0;
			led0_state <= led0_state + 1'b1;
		end else begin
			ctr <= ctr + 1'b1;
		end
	end

	ddr3l ram (
		.reset  (ddr3_reset),
		.odt    (ddr3_odt),
		.a0     (ddr3_a0),
		.a1     (ddr3_a1),
		.a2     (ddr3_a2),
		.a3     (ddr3_a3),
		.a4     (ddr3_a4),
		.a5     (ddr3_a5),
		.a6     (ddr3_a6),
		.a7     (ddr3_a7),
		.a8     (ddr3_a8),
		.a9     (ddr3_a9),
		.a10    (ddr3_a10),
		.a11    (ddr3_a11),
		.a12    (ddr3_a12),
		.a13    (ddr3_a13),
		.ba0    (ddr3_ba0),
		.ba1    (ddr3_ba1),
		.ba2    (ddr3_ba2),
		.cs     (ddr3_cs),
		.ras    (ddr3_ras),
		.cas    (ddr3_cas),
		.we     (ddr3_we),
		.cke0   (ddr3_cke0),
		.clk0_p (ddr3_clk0_p),
		.clk0_n (ddr3_clk0_n),
		.dm0    (ddr3_dm0),
		.dm1    (ddr3_dm1),
		.dq0    (ddr3_dq0),
		.dq1    (ddr3_dq1),
		.dq2    (ddr3_dq2),
		.dq3    (ddr3_dq3),
		.dq4    (ddr3_dq4),
		.dq5    (ddr3_dq5),
		.dq6    (ddr3_dq6),
		.dq7    (ddr3_dq7),
		.dq8    (ddr3_dq8),
		.dq9    (ddr3_dq9),
		.dq10   (ddr3_dq10),
		.dq11   (ddr3_dq11),
		.dq12   (ddr3_dq12),
		.dq13   (ddr3_dq13),
		.dq14   (ddr3_dq14),
		.dq15   (ddr3_dq15),
		.dqs0_p (ddr3_dqs0_p),
		.dqs0_n (ddr3_dqs0_n),
		.dqs1_p (ddr3_dqs1_p),
		.dqs1_n (ddr3_dqs1_n)
	);
endmodule