module pixelflut (
	input         sys_clk,

	output        led0_r,
	output        led0_g,
	output        led0_b,

	output [11:0] dvi_d,
	output        dvi_ck,
	output        dvi_de,
	output        dvi_hs,
	output        dvi_vs,

	output        eth_mdc,
	inout         eth_mdio,
	output        eth_ref_clk,
	output        eth_rstn,
	input         eth_rx_clk,
	input         eth_rx_dv,
	input   [3:0] eth_rxd,
	input         eth_rxerr,
	input         eth_tx_clk,
	output        eth_tx_en,
	output  [3:0] eth_txd,
);
	reg [31:0] ctr;
	reg  [2:0] led0_state;

	assign led0_r = led0_state[0];
	assign led0_g = led0_state[1];
	assign led0_b = led0_state[2];

	initial begin
		led0_state <= 3'b0;
	end

	always @(posedge sys_clk) begin
		if (ctr == 32'd50_000_000) begin
			ctr <= 32'b0;
			led0_state <= led0_state + 1'b1;
		end else begin
			ctr <= ctr + 1'b1;
		end
	end

	reg dvi_bus_clk;

	always @(posedge sys_clk) begin
		dvi_bus_clk <= ~dvi_bus_clk;
	end

	wire [15:0] dvi_bus_data;
	wire [23:0] dvi_bus_addr;

	dvi display (
		.bus_clk (dvi_bus_clk),
		.bus_data(dvi_bus_data),
		.bus_addr(dvi_bus_addr),
		.reset   (1'b0),
		.d       (dvi_d),
		.ck      (dvi_ck),
		.de      (dvi_de),
		.hs      (dvi_hs),
		.vs      (dvi_vs),
	);

	reg [1:0] eth_clk_div;

	assign eth_ref_clk = eth_clk_div[1];

	initial begin
		eth_clk_div <= 2'b0;
	end

	always @(posedge sys_clk) begin
		eth_clk_div <= eth_clk_div + 1;
	end

	assign eth_rstn  = 1;
	assign eth_tx_en = 0;
	assign eth_txd = 4'b0;

	wire eth_mdio_i, eth_mdio_o, eth_mdio_en;

	IOBUF eth_mdio_buf (
		.I (eth_mdio_o),
		.IO(eth_mdio),
		.O (eth_mdio_i),
		.T (eth_mdio_en),
	);

	ethernet_smi smi (
		.clk    (sys_clk),
		.mdio_i (eth_mdio_i),
		.mdio_o (eth_mdio_o),
		.mdio_en(eth_mdio_en),
		.mdc    (eth_mdc),
	);

	wire        eth_bus_clk;
	wire [15:0] eth_bus_data;
	wire [23:0] eth_bus_addr;
	wire  [1:0] eth_bus_sel;

	pingxelflut eth (
		.rx_clk  (eth_rx_clk),
		.rxd     (eth_rxd),
		.rx_dv   (eth_rx_dv),
		.rx_er   (eth_rxerr),
		.bus_clk (eth_bus_clk),
		.bus_data(eth_bus_data),
		.bus_addr(eth_bus_addr),
		.bus_sel (eth_bus_sel),
	);

	xc7_bram ram (
		.out_clk (dvi_bus_clk),
		.out_data(dvi_bus_data),
		.out_addr(dvi_bus_addr),
		.in_clk  (eth_bus_clk),
		.in_data (eth_bus_data),
		.in_addr (eth_bus_addr),
		.in_wren (eth_bus_sel),
	);
endmodule