module xc7_bram #(
	parameter NUM_BLOCKS = 50,
) (
	input         out_clk,
	output [15:0] out_data,
	input  [23:0] out_addr,

	input         in_clk,
	input  [15:0] in_data,
	input  [23:0] in_addr,
	input   [1:0] in_wren,
);
	wire [31:0] porta_out [NUM_BLOCKS-1:0];
	wire [15:0] porta_addr, portb_addr;

	assign out_data = porta_out[out_addr[16:11]][15:0];

	assign porta_addr = {1'b1, out_addr[10:0], 4'b1};
	assign portb_addr = {1'b1, in_addr[10:0], 4'b1};

	genvar i;

	generate
		for (i = 0; i < NUM_BLOCKS; i = i + 1) begin
			RAMB36E1 #(
				.READ_WIDTH_A (18),
				.WRITE_WIDTH_B(18),
			) bram_block (
				.DOADO      (porta_out[i]),
				.ADDRARDADDR(porta_addr),
				.CLKARDCLK  (out_clk),
				.ENARDEN    (1'b1),
				.ADDRBWRADDR(portb_addr),
				.CLKBWRCLK  (in_clk),
				.ENBWREN    (in_addr[16:11] == i),
				.WEBWE      ({6'b0, in_wren}),
				.DIBDI      ({16'h0000, in_data}),
			);
		end
	endgenerate
endmodule