From a362cff8caa5d5b0bfdc6f888923c4dba511d210 Mon Sep 17 00:00:00 2001 From: Luca Date: Fri, 18 Oct 2024 23:58:44 +0200 Subject: [PATCH] chore: remove DDR3L instantiation for now --- Makefile | 2 +- pixelflut.v | 176 ---------------------------------------------------- 2 files changed, 1 insertion(+), 177 deletions(-) diff --git a/Makefile b/Makefile index 13faaca..647eb2e 100644 --- a/Makefile +++ b/Makefile @@ -22,5 +22,5 @@ pixelflut.frames: pixelflut.fasm pixelflut.fasm: arty_a7_35t.xdc pixelflut.json nextpnr-xilinx --chipdb "$(CHIPDB_DIR)/$(PART).bin" --fasm $@ --json pixelflut.json --xdc arty_a7_35t.xdc -pixelflut.json: pixelflut.v ddr3l.v +pixelflut.json: pixelflut.v yosys -q -p 'synth_xilinx -top pixelflut; write_json $@' $^ diff --git a/pixelflut.v b/pixelflut.v index 1d8b712..1e517cb 100644 --- a/pixelflut.v +++ b/pixelflut.v @@ -4,24 +4,6 @@ module pixelflut ( output led0_r, output led0_g, output led0_b, - - output ddr3_reset, - output ddr3_odt, - output [13:0] ddr3_a, - output [2:0] ddr3_ba, - output ddr3_cs, - output ddr3_ras, - output ddr3_cas, - output ddr3_we, - output ddr3_cke0, - output ddr3_clk0_p, - output ddr3_clk0_n, - output [1:0] ddr3_dm, - inout [15:0] ddr3_dq, - inout ddr3_dqs0_p, - inout ddr3_dqs0_n, - inout ddr3_dqs1_p, - inout ddr3_dqs1_n, ); reg [31:0] ctr; reg [2:0] led0_state = 3'b0; @@ -38,162 +20,4 @@ module pixelflut ( ctr <= ctr + 1'b1; end end - - wire ddr3_clk, ddr3_dq_en, ddr3_dqs_en; - wire [15:0] ddr3_dq_i, ddr3_dq_o; - wire [1:0] ddr3_dqs_i, ddr3_dqs_o; - - OBUFDS ddr3_clk0 ( - .I (ddr3_clk), - .O (ddr3_clk0_p), - .OB(ddr3_clk0_n), - ); - - IOBUF ddr3_dq0 ( - .I (ddr3_dq_o[0]), - .IO(ddr3_dq[0]), - .O (ddr3_dq_i[0]), - .T (ddr3_dq_en), - ); - - IOBUF ddr3_dq1 ( - .I (ddr3_dq_o[1]), - .IO(ddr3_dq[1]), - .O (ddr3_dq_i[1]), - .T (ddr3_dq_en), - ); - - IOBUF ddr3_dq2 ( - .I (ddr3_dq_o[2]), - .IO(ddr3_dq[2]), - .O (ddr3_dq_i[2]), - .T (ddr3_dq_en), - ); - - IOBUF ddr3_dq3 ( - .I (ddr3_dq_o[3]), - .IO(ddr3_dq[3]), - .O (ddr3_dq_i[3]), - .T (ddr3_dq_en), - ); - - IOBUF ddr3_dq4 ( - .I (ddr3_dq_o[4]), - .IO(ddr3_dq[4]), - .O (ddr3_dq_i[4]), - .T (ddr3_dq_en), - ); - - IOBUF ddr3_dq5 ( - .I (ddr3_dq_o[5]), - .IO(ddr3_dq[5]), - .O (ddr3_dq_i[5]), - .T (ddr3_dq_en), - ); - - IOBUF ddr3_dq6 ( - .I (ddr3_dq_o[6]), - .IO(ddr3_dq[6]), - .O (ddr3_dq_i[6]), - .T (ddr3_dq_en), - ); - - IOBUF ddr3_dq7 ( - .I (ddr3_dq_o[7]), - .IO(ddr3_dq[7]), - .O (ddr3_dq_i[7]), - .T (ddr3_dq_en), - ); - - IOBUF ddr3_dq8 ( - .I (ddr3_dq_o[8]), - .IO(ddr3_dq[8]), - .O (ddr3_dq_i[8]), - .T (ddr3_dq_en), - ); - - IOBUF ddr3_dq9 ( - .I (ddr3_dq_o[9]), - .IO(ddr3_dq[9]), - .O (ddr3_dq_i[9]), - .T (ddr3_dq_en), - ); - - IOBUF ddr3_dq10 ( - .I (ddr3_dq_o[10]), - .IO(ddr3_dq[10]), - .O (ddr3_dq_i[10]), - .T (ddr3_dq_en), - ); - - IOBUF ddr3_dq11 ( - .I (ddr3_dq_o[11]), - .IO(ddr3_dq[11]), - .O (ddr3_dq_i[11]), - .T (ddr3_dq_en), - ); - - IOBUF ddr3_dq12 ( - .I (ddr3_dq_o[12]), - .IO(ddr3_dq[12]), - .O (ddr3_dq_i[12]), - .T (ddr3_dq_en), - ); - - IOBUF ddr3_dq13 ( - .I (ddr3_dq_o[13]), - .IO(ddr3_dq[13]), - .O (ddr3_dq_i[13]), - .T (ddr3_dq_en), - ); - - IOBUF ddr3_dq14 ( - .I (ddr3_dq_o[14]), - .IO(ddr3_dq[14]), - .O (ddr3_dq_i[14]), - .T (ddr3_dq_en), - ); - - IOBUF ddr3_dq15 ( - .I (ddr3_dq_o[15]), - .IO(ddr3_dq[15]), - .O (ddr3_dq_i[15]), - .T (ddr3_dq_en), - ); - - IOBUFDS ddr3_dqs0 ( - .I (ddr3_dqs_o[0]), - .IO (ddr3_dqs0_p), - .IOB(ddr3_dqs0_n), - .O (ddr3_dqs_i[0]), - .T (ddr3_dqs_en), - ); - - IOBUFDS ddr3_dqs1 ( - .I (ddr3_dqs_o[1]), - .IO (ddr3_dqs1_p), - .IOB(ddr3_dqs1_n), - .O (ddr3_dqs_i[1]), - .T (ddr3_dqs_en), - ); - - ddr3l ram ( - .reset (ddr3_reset), - .odt (ddr3_odt), - .a (ddr3_a), - .ba (ddr3_ba), - .cs (ddr3_cs), - .ras (ddr3_ras), - .cas (ddr3_cas), - .we (ddr3_we), - .cke (ddr3_cke0), - .clk (ddr3_clk), - .dm (ddr3_dm), - .dq_i (ddr3_dq_i), - .dq_o (ddr3_dq_o), - .dq_en (ddr3_dq_en), - .dqs_i (ddr3_dqs_i), - .dqs_o (ddr3_dqs_o), - .dqs_en(ddr3_dqs_en), - ); endmodule