From 6b988087bd470501f0ad5f9dfc4dbcd6ccfd08e7 Mon Sep 17 00:00:00 2001
From: Luca <Luca@hackerspace-bamberg.de>
Date: Fri, 25 Oct 2024 20:27:37 +0200
Subject: [PATCH] feat: use BRAM as video memory

---
 Makefile    |  2 +-
 pixelflut.v | 10 ++++++++++
 xc7_bram.v  | 41 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 52 insertions(+), 1 deletion(-)
 create mode 100644 xc7_bram.v

diff --git a/Makefile b/Makefile
index a4ae98e..0826893 100644
--- a/Makefile
+++ b/Makefile
@@ -26,7 +26,7 @@ pixelflut.frames: pixelflut.fasm
 pixelflut.fasm: arty_a7_35t.xdc pixelflut.json
 	nextpnr-xilinx --chipdb "$(CHIPDB_DIR)/$(PART).bin" --fasm $@ --json pixelflut.json --xdc arty_a7_35t.xdc
 
-pixelflut.json: pixelflut.v dvi.v
+pixelflut.json: pixelflut.v dvi.v xc7_bram.v
 	yosys -q -p 'synth_xilinx -top pixelflut; write_json $@' $^
 
 dvi_tb.vcd: dvi_tb.vvp
diff --git a/pixelflut.v b/pixelflut.v
index aeced6b..37fe57d 100644
--- a/pixelflut.v
+++ b/pixelflut.v
@@ -47,4 +47,14 @@ module pixelflut (
 		.hs      (dvi_hs),
 		.vs      (dvi_vs),
 	);
+
+	xc7_bram ram (
+		.out_clk (dvi_bus_clk),
+		.out_data(dvi_bus_data),
+		.out_addr(dvi_bus_addr),
+		.in_clk  (),
+		.in_data (),
+		.in_addr (),
+		.in_wren (),
+	);
 endmodule
diff --git a/xc7_bram.v b/xc7_bram.v
new file mode 100644
index 0000000..0c1b749
--- /dev/null
+++ b/xc7_bram.v
@@ -0,0 +1,41 @@
+module xc7_bram #(
+	parameter NUM_BLOCKS = 50,
+) (
+	input         out_clk,
+	output [15:0] out_data,
+	input  [23:0] out_addr,
+
+	input         in_clk,
+	input  [15:0] in_data,
+	input  [23:0] in_addr,
+	input   [1:0] in_wren,
+);
+	wire [31:0] porta_out [NUM_BLOCKS-1:0];
+	wire [15:0] porta_addr, portb_addr;
+
+	assign out_data = porta_out[out_addr[16:11]][15:0];
+
+	assign porta_addr = {1'b1, out_addr[10:0], 4'b1};
+	assign portb_addr = {1'b1, in_addr[10:0], 4'b1};
+
+	genvar i;
+
+	generate
+		for (i = 0; i < NUM_BLOCKS; i = i + 1) begin
+			RAMB36E1 #(
+				.READ_WIDTH_A (18),
+				.WRITE_WIDTH_B(18),
+			) bram_block (
+				.DOADO      (porta_out[i]),
+				.ADDRARDADDR(porta_addr),
+				.CLKARDCLK  (out_clk),
+				.ENARDEN    (1'b1),
+				.ADDRBWRADDR(portb_addr),
+				.CLKBWRCLK  (in_clk),
+				.ENBWREN    (in_addr[16:11] == i),
+				.WEBWE      ({6'b0, in_wren}),
+				.DIBDI      ({16'h0000, in_data}),
+			);
+		end
+	endgenerate
+endmodule