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# For PCBs designed using KiCad: https://www.kicad.org/
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# Format documentation: https://kicad.org/help/file-formats/
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# Temporary files
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*.000
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*.bak
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*.bck
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*.kicad_pcb-bak
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*.kicad_sch-bak
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*-backups
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*.kicad_prl
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*.sch-bak
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*~
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_autosave-*
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*.tmp
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*-save.pro
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*-save.kicad_pcb
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fp-info-cache
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# Netlist files (exported from Eeschema)
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*.net
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# Autorouter files (exported from Pcbnew)
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*.dsn
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*.ses
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# Exported BOM files
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*.xml
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*.csv
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(kicad_pcb (version 20211014) (generator pcbnew)
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)
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{
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"board": {
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"design_settings": {
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"defaults": {
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"board_outline_line_width": 0.1,
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"copper_line_width": 0.2,
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"copper_text_size_h": 1.5,
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"copper_text_size_v": 1.5,
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"copper_text_thickness": 0.3,
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"other_line_width": 0.15,
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"silk_line_width": 0.15,
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"silk_text_size_h": 1.0,
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"silk_text_size_v": 1.0,
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"silk_text_thickness": 0.15
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},
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"diff_pair_dimensions": [],
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"drc_exclusions": [],
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"rules": {
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"min_copper_edge_clearance": 0.0,
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"solder_mask_clearance": 0.0,
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"solder_mask_min_width": 0.0
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},
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"track_widths": [],
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"via_dimensions": []
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}
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},
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"boards": [],
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"libraries": {
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"pinned_footprint_libs": [],
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"pinned_symbol_libs": []
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},
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"meta": {
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"filename": "kicad.kicad_pro",
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"version": 1
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},
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"net_settings": {
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"classes": [
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{
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"clearance": 0.2,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"name": "Default",
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"nets": [],
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"track_width": 0.25,
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"via_diameter": 0.8,
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"via_drill": 0.4
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}
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],
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"meta": {
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"version": 0
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}
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},
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"pcbnew": {
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"page_layout_descr_file": ""
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},
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"sheets": [],
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"text_variables": {}
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}
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(kicad_sch (version 20211123) (generator eeschema)
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(paper "A4")
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(lib_symbols)
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(symbol_instances)
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)
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