From 9b45732d051102853bbe448637553a2e963a8d05 Mon Sep 17 00:00:00 2001 From: Luca Date: Sun, 27 Feb 2022 20:24:26 +0100 Subject: [PATCH] Lower minimum clearance to pass DRC --- microsd-breakout.kicad_pcb | 304 ++++++++++++++++++++++++++++++++++++- microsd-breakout.kicad_pro | 2 +- 2 files changed, 301 insertions(+), 5 deletions(-) diff --git a/microsd-breakout.kicad_pcb b/microsd-breakout.kicad_pcb index 4a05bb1..4b17b8e 100644 --- a/microsd-breakout.kicad_pcb +++ b/microsd-breakout.kicad_pcb @@ -25,13 +25,13 @@ (setup (stackup - (layer "F.SilkS" (type "Top Silk Screen")) - (layer "F.Mask" (type "Top Solder Mask") (thickness 0.01)) + (layer "F.SilkS" (type "Top Silk Screen") (color "White")) + (layer "F.Mask" (type "Top Solder Mask") (color "Purple") (thickness 0.01)) (layer "F.Cu" (type "copper") (thickness 0.035)) (layer "dielectric 1" (type "core") (thickness 0.71) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02)) (layer "B.Cu" (type "copper") (thickness 0.035)) - (layer "B.Mask" (type "Bottom Solder Mask") (thickness 0.01)) - (layer "B.SilkS" (type "Bottom Silk Screen")) + (layer "B.Mask" (type "Bottom Solder Mask") (color "Purple") (thickness 0.01)) + (layer "B.SilkS" (type "Bottom Silk Screen") (color "White")) (copper_finish "ENIG") (dielectric_constraints no) ) @@ -198,6 +198,19 @@ ) ) + (gr_text "JLCJLCJLCJLC" (at 156 100.35 -90) (layer "B.SilkS") (tstamp 5750479a-4964-417a-b1bf-44db3c1e2f5b) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror)) + ) + (gr_text "lujoga" (at 145 104.5 -90) (layer "B.SilkS") (tstamp 71a1745e-502c-487f-a487-540eff6b8593) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify left mirror)) + ) + (gr_text "2022" (at 145 94.85 -90) (layer "B.SilkS") (tstamp 7ea018fc-7e7e-4010-8dff-30ceba87bdba) + (effects (font (size 0.8 0.8) (thickness 0.1)) (justify right mirror)) + ) + (gr_text "microSD\nbreakout\nboard" (at 149.5 100.35 -90) (layer "B.SilkS") (tstamp e378f79b-a86f-43bb-aefe-4305866fd904) + (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) + ) + (segment (start 152.35 104.2) (end 154.35 104.2) (width 0.25) (layer "F.Cu") (net 1) (tstamp 4642087a-c327-4b0a-bce0-bf74f11b64df)) (segment (start 143.3 103.85) (end 152 103.85) (width 0.25) (layer "F.Cu") (net 1) (tstamp ec89862f-44dc-46ab-a3d6-4a338da58ff7)) (segment (start 152 103.85) (end 152.35 104.2) (width 0.25) (layer "F.Cu") (net 1) (tstamp f197772a-d51a-45ed-8acd-d64d67eb8400)) @@ -223,4 +236,287 @@ (segment (start 152.35 96.5) (end 154.35 96.5) (width 0.25) (layer "F.Cu") (net 8) (tstamp 9d54256c-48b7-4895-8212-6184519dabec)) (segment (start 152 96.85) (end 152.35 96.5) (width 0.25) (layer "F.Cu") (net 8) (tstamp dd3d91cf-e9fe-4646-b961-7c07791521fa)) + (zone (net 3) (net_name "Net-(J1-Pad3)") (layer "B.Cu") (tstamp b29ec5fc-7c8c-461d-9bc9-c438cef53a8c) (hatch edge 0.508) + (connect_pads (clearance 0.508)) + (min_thickness 0.254) (filled_areas_thickness no) + (fill yes (thermal_gap 0.508) (thermal_bridge_width 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