From d03fd3361d47833757973127f4d4c1ba6135a933 Mon Sep 17 00:00:00 2001 From: Luca Date: Wed, 19 Oct 2022 23:50:28 +0200 Subject: [PATCH] Fit all components on pcb --- ethernet-pmod.kicad_pcb | 2522 ++++++++++++++++++++++++++++++++++++++- ethernet-pmod.kicad_pro | 25 +- 2 files changed, 2540 insertions(+), 7 deletions(-) diff --git a/ethernet-pmod.kicad_pcb b/ethernet-pmod.kicad_pcb index 28b47a1..2e61afc 100644 --- a/ethernet-pmod.kicad_pcb +++ b/ethernet-pmod.kicad_pcb @@ -1,2 +1,2522 @@ (kicad_pcb (version 20211014) (generator pcbnew) -) \ No newline at end of file + + (general + (thickness 1.6) + ) + + (paper "A4") + (layers + (0 "F.Cu" signal) + (31 "B.Cu" signal) + (32 "B.Adhes" user "B.Adhesive") + (33 "F.Adhes" user "F.Adhesive") + (34 "B.Paste" user) + (35 "F.Paste" user) + (36 "B.SilkS" user "B.Silkscreen") + (37 "F.SilkS" user "F.Silkscreen") + (38 "B.Mask" user) + (39 "F.Mask" user) + (40 "Dwgs.User" user "User.Drawings") + (41 "Cmts.User" user "User.Comments") + (42 "Eco1.User" user "User.Eco1") + (43 "Eco2.User" user "User.Eco2") + (44 "Edge.Cuts" user) + (45 "Margin" user) + (46 "B.CrtYd" user "B.Courtyard") + (47 "F.CrtYd" user "F.Courtyard") + (48 "B.Fab" user) + (49 "F.Fab" user) + (50 "User.1" user) + (51 "User.2" user) + (52 "User.3" user) + (53 "User.4" user) + (54 "User.5" user) + (55 "User.6" user) + (56 "User.7" user) + (57 "User.8" user) + (58 "User.9" user) + ) + + (setup + (stackup + (layer "F.SilkS" (type "Top Silk Screen")) + (layer "F.Paste" (type "Top Solder Paste")) + (layer "F.Mask" (type "Top Solder Mask") (thickness 0.01)) + (layer "F.Cu" (type "copper") (thickness 0.035)) + (layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02)) + (layer "B.Cu" (type "copper") (thickness 0.035)) + (layer "B.Mask" (type "Bottom Solder Mask") (thickness 0.01)) + (layer "B.Paste" (type "Bottom Solder Paste")) + (layer "B.SilkS" (type "Bottom Silk Screen")) + (copper_finish "HAL lead-free") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (pcbplotparams + (layerselection 0x00010fc_ffffffff) + (disableapertmacros false) + (usegerberextensions false) + (usegerberattributes true) + (usegerberadvancedattributes true) + (creategerberjobfile true) + (svguseinch false) + (svgprecision 6) + (excludeedgelayer true) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (dxfpolygonmode true) + (dxfimperialunits true) + (dxfusepcbnewfont true) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (sketchpadsonfab false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + + (net 0 "") + (net 1 "+1V2") + (net 2 "GND") + (net 3 "VDDA") + (net 4 "+3V3") + (net 5 "Net-(C7-Pad1)") + (net 6 "Net-(C7-Pad2)") + (net 7 "VDC") + (net 8 "GND1") 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110.146447 87.646447) (end 110.5 87.5) (layer "Edge.Cuts") (width 0.1) (tstamp bd0f7918-d1af-4a58-8a81-84ecff580770)) + (gr_line (start 110 88) (end 110 112) (layer "Edge.Cuts") (width 0.1) (tstamp ef6d9a30-d751-4692-98e4-c6aaec6df432)) + (gr_text "Ethernet Pmod\nv1" (at 110.5 89.7) (layer "F.SilkS") (tstamp 26f739ef-9b16-4e32-b3a8-47bf49a8fc19) + (effects (font (size 1.2 1.2) (thickness 0.18)) (justify left)) + ) + (gr_text "lujoga 2022" (at 110.5 111) (layer "F.SilkS") (tstamp 4d0b6203-bce9-455d-a850-93c4d816b539) + (effects (font (size 1 1) (thickness 0.15)) (justify left)) + ) + (gr_text "JLCJLCJLCJLC" (at 130 100 90) (layer "F.SilkS") (tstamp 99e86908-ec7f-4cc6-a39a-a78be558ca0a) + (effects (font (size 1 1) (thickness 0.15))) + ) + +) diff --git a/ethernet-pmod.kicad_pro b/ethernet-pmod.kicad_pro index ada2251..eb14879 100644 --- a/ethernet-pmod.kicad_pro +++ b/ethernet-pmod.kicad_pro @@ -33,9 +33,9 @@ "other_text_thickness": 0.15, "other_text_upright": false, "pads": { - "drill": 0.762, - "height": 1.524, - "width": 1.524 + "drill": 0.0, + "height": 0.64, + "width": 0.54 }, "silk_line_width": 0.15, "silk_text_italic": false, @@ -48,7 +48,13 @@ "min_clearance": 0.508 } }, - "diff_pair_dimensions": [], + "diff_pair_dimensions": [ + { + "gap": 0.0, + "via_gap": 0.0, + "width": 0.0 + } + ], "drc_exclusions": [], "meta": { "version": 2 @@ -112,8 +118,15 @@ "solder_mask_min_width": 0.0, "use_height_for_length_calcs": true }, - "track_widths": [], - "via_dimensions": [], + "track_widths": [ + 0.0 + ], + "via_dimensions": [ + { + "diameter": 0.0, + "drill": 0.0 + } + ], "zones_allow_external_fillets": false, "zones_use_no_outline": true },