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Make vias as small as JLCPCB can fabricate

This commit is contained in:
Luca 2020-10-25 17:41:50 +01:00
parent eb58c33724
commit 8ba2758278
2 changed files with 9 additions and 9 deletions
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8
anykey.kicad_pcb
View File

@ -39,8 +39,8 @@
(zone_clearance 0.508)
(zone_45_only no)
(trace_min 0.2)
(via_size 0.8)
(via_drill 0.4)
(via_size 0.6)
(via_drill 0.3)
(via_min_size 0.6)
(via_min_drill 0.3)
(uvia_size 0.3)
@ -141,8 +141,8 @@
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.2)
(via_dia 0.8)
(via_drill 0.4)
(via_dia 0.6)
(via_drill 0.3)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net +3V3)

10
anykey.pro
View File

@ -1,4 +1,4 @@
update=Sa 24 Okt 2020 20:09:03 CEST
update=So 25 Okt 2020 17:40:24 CET
version=1
last_client=kicad
[general]
@ -39,8 +39,8 @@ MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.2
ViaDiameter1=0.8
ViaDrill1=0.4
ViaDiameter1=0.6
ViaDrill1=0.3
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
@ -239,8 +239,8 @@ Enabled=0
Name=Default
Clearance=0.2
TrackWidth=0.2
ViaDiameter=0.8
ViaDrill=0.4
ViaDiameter=0.6
ViaDrill=0.3
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2